dpram_u1k1.tdf
来自「双口RAM与PXI总线接口设计」· TDF 代码 · 共 55 行
TDF
55 行
--altdpram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" INDATA_ACLR="OFF" INDATA_REG="INCLOCK" INTENDED_DEVICE_FAMILY="Cyclone" NUMWORDS=2048 OUTDATA_ACLR="OFF" OUTDATA_REG="OUTCLOCK" RDADDRESS_ACLR="OFF" RDADDRESS_REG="OUTCLOCK" RDCONTROL_ACLR="OFF" RDCONTROL_REG="OUTCLOCK" USE_EAB="ON" WIDTH=8 WIDTHAD=11 WRADDRESS_ACLR="OFF" WRADDRESS_REG="INCLOCK" WRCONTROL_ACLR="OFF" WRCONTROL_REG="INCLOCK" data inclock outclock q rdaddress rden wraddress wren CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 7.2 cbx_altdpram 2007:04:25:14:55:30:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ VERSION_END
-- Copyright (C) 1991-2007 Altera Corporation
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-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION altsyncram_f6p1 (address_a[10..0], address_b[10..0], clock0, clock1, data_a[7..0], rden_b, wren_a)
RETURNS ( q_b[7..0]);
--synthesis_resources = M4K 4
SUBDESIGN dpram_u1k1
(
data[7..0] : input;
inclock : input;
outclock : input;
q[7..0] : output;
rdaddress[10..0] : input;
rden : input;
wraddress[10..0] : input;
wren : input;
)
VARIABLE
altsyncram1 : altsyncram_f6p1;
BEGIN
altsyncram1.address_a[] = wraddress[];
altsyncram1.address_b[] = rdaddress[];
altsyncram1.clock0 = inclock;
altsyncram1.clock1 = outclock;
altsyncram1.data_a[] = data[];
altsyncram1.rden_b = rden;
altsyncram1.wren_a = wren;
q[] = altsyncram1.q_b[];
ASSERT (0)
REPORT "DUAL PORT RAM for Stratix not possible thru altsyncram. Implementing using benchmarking mode, trying to tie up the inputs using available clocks. Output behavior will not be the same"
SEVERITY WARNING;
ASSERT (0)
REPORT "inclock is used to clock all inputs to the Stratix dual port ram"
SEVERITY INFO;
END;
--VALID FILE
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