prev_cmp_pxi_dsp_da.tan.qmsg

双口RAM与PXI总线接口设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "R/W memory ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\] memory ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~porta_datain_reg0 219.3 MHz 4.56 ns Internal " "Info: Clock \"R/W\" has Internal fmax of 219.3 MHz between source memory \"ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\]\" and destination memory \"ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~porta_datain_reg0\" (period= 4.56 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.552 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.552 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 0.080 ns ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\] 1 MEM M4K_X17_Y18 2 " "Info: 1: + IC(0.000 ns) + CELL(0.080 ns) = 0.080 ns; Loc. = M4K_X17_Y18; Fanout = 2; MEM Node = 'ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "db/altsyncram_5bp1.tdf" "" { Text "C:/quartus60/protect/RAM/db/altsyncram_5bp1.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.015 ns) + CELL(0.225 ns) 2.320 ns tri_s8:inst10\|odata365\[7\]~312 2 COMB LC_X11_Y13_N0 2 " "Info: 2: + IC(2.015 ns) + CELL(0.225 ns) = 2.320 ns; Loc. = LC_X11_Y13_N0; Fanout = 2; COMB Node = 'tri_s8:inst10\|odata365\[7\]~312'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] tri_s8:inst10|odata365[7]~312 } "NODE_NAME" } } { "tri_s8.vhd" "" { Text "C:/quartus60/protect/RAM/tri_s8.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.958 ns) + CELL(0.274 ns) 4.552 ns ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~porta_datain_reg0 3 MEM M4K_X17_Y18 1 " "Info: 3: + IC(1.958 ns) + CELL(0.274 ns) = 4.552 ns; Loc. = M4K_X17_Y18; Fanout = 1; MEM Node = 'ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~porta_datain_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { tri_s8:inst10|odata365[7]~312 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_5bp1.tdf" "" { Text "C:/quartus60/protect/RAM/db/altsyncram_5bp1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.579 ns ( 12.72 % ) " "Info: Total cell delay = 0.579 ns ( 12.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.973 ns ( 87.28 % ) " "Info: Total interconnect delay = 3.973 ns ( 87.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.552 ns" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] tri_s8:inst10|odata365[7]~312 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.552 ns" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] {} tri_s8:inst10|odata365[7]~312 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 {} } { 0.000ns 2.015ns 1.958ns } { 0.080ns 0.225ns 0.274ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.564 ns - Smallest " "Info: - Smallest clock skew is 0.564 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "R/W destination 6.677 ns + Shortest memory " "Info: + Shortest clock path from clock \"R/W\" to destination memory is 6.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns R/W 1 CLK PIN_23 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'R/W'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { R/W } "NODE_NAME" } } { "pxi_dsp_da.bdf" "" { Schematic "C:/quartus60/protect/RAM/pxi_dsp_da.bdf" { { 272 -136 32 288 "R/W" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.438 ns) + CELL(0.225 ns) 2.793 ns log_ctrl_m:inst\|inst3 2 COMB LC_X11_Y13_N1 128 " "Info: 2: + IC(1.438 ns) + CELL(0.225 ns) = 2.793 ns; Loc. = LC_X11_Y13_N1; Fanout = 128; COMB Node = 'log_ctrl_m:inst\|inst3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { R/W log_ctrl_m:inst|inst3 } "NODE_NAME" } } { "log_ctrl_m.bdf" "" { Schematic "C:/quartus60/protect/RAM/log_ctrl_m.bdf" { { 160 320 384 208 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.328 ns) + CELL(0.556 ns) 6.677 ns ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~porta_datain_reg0 3 MEM M4K_X17_Y18 1 " "Info: 3: + IC(3.328 ns) + CELL(0.556 ns) = 6.677 ns; Loc. = M4K_X17_Y18; Fanout = 1; MEM Node = 'ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~porta_datain_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.884 ns" { log_ctrl_m:inst|inst3 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_5bp1.tdf" "" { Text "C:/quartus60/protect/RAM/db/altsyncram_5bp1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 28.62 % ) " "Info: Total cell delay = 1.911 ns ( 28.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.766 ns ( 71.38 % ) " "Info: Total interconnect delay = 4.766 ns ( 71.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.677 ns" { R/W log_ctrl_m:inst|inst3 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.677 ns" { R/W {} R/W~out0 {} log_ctrl_m:inst|inst3 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 {} } { 0.000ns 0.000ns 1.438ns 3.328ns } { 0.000ns 1.130ns 0.225ns 0.556ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "R/W source 6.113 ns - Longest memory " "Info: - Longest clock path from clock \"R/W\" to source memory is 6.113 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns R/W 1 CLK PIN_23 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 6; CLK Node = 'R/W'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { R/W } "NODE_NAME" } } { "pxi_dsp_da.bdf" "" { Schematic "C:/quartus60/protect/RAM/pxi_dsp_da.bdf" { { 272 -136 32 288 "R/W" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.531 ns) + CELL(0.225 ns) 2.886 ns log_ctrl_m:inst\|inst4 2 COMB LC_X8_Y10_N2 112 " "Info: 2: + IC(1.531 ns) + CELL(0.225 ns) = 2.886 ns; Loc. = LC_X8_Y10_N2; Fanout = 112; COMB Node = 'log_ctrl_m:inst\|inst4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.756 ns" { R/W log_ctrl_m:inst|inst4 } "NODE_NAME" } } { "log_ctrl_m.bdf" "" { Schematic "C:/quartus60/protect/RAM/log_ctrl_m.bdf" { { 256 232 296 304 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.686 ns) + CELL(0.541 ns) 6.113 ns ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\] 3 MEM M4K_X17_Y18 2 " "Info: 3: + IC(2.686 ns) + CELL(0.541 ns) = 6.113 ns; Loc. = M4K_X17_Y18; Fanout = 2; MEM Node = 'ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.227 ns" { log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "db/altsyncram_5bp1.tdf" "" { Text "C:/quartus60/protect/RAM/db/altsyncram_5bp1.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.896 ns ( 31.02 % ) " "Info: Total cell delay = 1.896 ns ( 31.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.217 ns ( 68.98 % ) " "Info: Total interconnect delay = 4.217 ns ( 68.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.113 ns" { R/W log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.113 ns" { R/W {} R/W~out0 {} log_ctrl_m:inst|inst4 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] {} } { 0.000ns 0.000ns 1.531ns 2.686ns } { 0.000ns 1.130ns 0.225ns 0.541ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.677 ns" { R/W log_ctrl_m:inst|inst3 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.677 ns" { R/W {} R/W~out0 {} log_ctrl_m:inst|inst3 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 {} } { 0.000ns 0.000ns 1.438ns 3.328ns } { 0.000ns 1.130ns 0.225ns 0.556ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.113 ns" { R/W log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.113 ns" { R/W {} R/W~out0 {} log_ctrl_m:inst|inst4 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] {} } { 0.000ns 0.000ns 1.531ns 2.686ns } { 0.000ns 1.130ns 0.225ns 0.541ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "db/altsyncram_5bp1.tdf" "" { Text "C:/quartus60/protect/RAM/db/altsyncram_5bp1.tdf" 34 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.072 ns + " "Info: + Micro setup delay of destination is 0.072 ns" {  } { { "db/altsyncram_5bp1.tdf" "" { Text "C:/quartus60/protect/RAM/db/altsyncram_5bp1.tdf" 256 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.552 ns" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] tri_s8:inst10|odata365[7]~312 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.552 ns" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] {} tri_s8:inst10|odata365[7]~312 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 {} } { 0.000ns 2.015ns 1.958ns } { 0.080ns 0.225ns 0.274ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.677 ns" { R/W log_ctrl_m:inst|inst3 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.677 ns" { R/W {} R/W~out0 {} log_ctrl_m:inst|inst3 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~porta_datain_reg0 {} } { 0.000ns 0.000ns 1.438ns 3.328ns } { 0.000ns 1.130ns 0.225ns 0.556ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.113 ns" { R/W log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.113 ns" { R/W {} R/W~out0 {} log_ctrl_m:inst|inst4 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] {} } { 0.000ns 0.000ns 1.531ns 2.686ns } { 0.000ns 1.130ns 0.225ns 0.541ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "A13 memory ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~porta_datain_reg0 memory ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~porta_memory_reg0 256.02 MHz 3.906 ns Internal " "Info: Clock \"A13\" has Internal fmax of 256.02 MHz between source memory \"ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~porta_datain_reg0\" and destination memory \"ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~porta_memory_reg0\" (period= 3.906 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.323 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~porta_datain_reg0 1 MEM M4K_X17_Y18 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y18; Fanout = 1; MEM Node = 'ram2:inst3\|alt3pram:alt3pra