tri_s11_1.vhd

来自「双口RAM与PXI总线接口设计」· VHDL 代码 · 共 15 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tri_s11_1 IS
port ( enaddr1 :IN STD_LOGIC;
	iaddrDSP : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	oaddrDSP : OUT STD_LOGIC_VECTOR(10 DOWNTO 0));
END  tri_s11_1;
ARCHITECTURE bhv OF tri_s11_1 IS
BEGIN
PROCESS(enaddr1,iaddrDSP)
BEGIN
IF enaddr1 = '1' THEN oaddrDSP <= iaddrDSP ;
ELSE oaddrDSP <="ZZZZZZZZZZZ" ; END IF ;
END PROCESS;
END bhv;