tri_s8_1.map.rpt

双口RAM与PXI总线接口设计

+--------------------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                       ;
+----------------------------------+-----------------+-----------------+---------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path          ;
+----------------------------------+-----------------+-----------------+---------------------------------------+
; tri_s8_1.vhd                     ; yes             ; User VHDL File  ; C:/quartus60/protect/RAM/tri_s8_1.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Total logic elements                        ; 0       ;
;     -- Combinational with no register       ; 0       ;
;     -- Register only                        ; 0       ;
;     -- Combinational with a register        ; 0       ;
;                                             ;         ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 0       ;
;     -- 3 input functions                    ; 0       ;
;     -- 2 input functions                    ; 0       ;
;     -- 1 input functions                    ; 0       ;
;     -- 0 input functions                    ; 0       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 0       ;
;     -- arithmetic mode                      ; 0       ;
;     -- qfbk mode                            ; 0       ;
;     -- register cascade mode                ; 0       ;
;     -- synchronous clear/load mode          ; 0       ;
;     -- asynchronous clear/load mode         ; 0       ;
;                                             ;         ;
; Total registers                             ; 0       ;
; I/O pins                                    ; 17      ;
; Maximum fan-out node                        ; endata3 ;
; Maximum fan-out                             ; 8       ;
; Total fan-out                               ; 16      ;
; Average fan-out                             ; 0.94    ;
+---------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |tri_s8_1                  ; 0 (0)       ; 0            ; 0           ; 17   ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |tri_s8_1           ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Thu Oct 04 17:12:18 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off tri_s8_1 -c tri_s8_1
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Found 2 design units, including 1 entities, in source file cnt12.vhd
    Info: Found design unit 1: CNT12-behav
    Info: Found entity 1: CNT12
Info: Found 1 design units, including 1 entities, in source file log_ctrl_da.bdf
    Info: Found entity 1: log_ctrl_da
Info: Found 1 design units, including 1 entities, in source file log_ctrl_m.bdf
    Info: Found entity 1: log_ctrl_m
Info: Found 1 design units, including 1 entities, in source file pxi_dsp_da.bdf
    Info: Found entity 1: pxi_dsp_da
Info: Found 2 design units, including 1 entities, in source file ram2.vhd
    Info: Found design unit 1: ram2-SYN
    Info: Found entity 1: ram2
Info: Found 2 design units, including 1 entities, in source file ram_da.vhd
    Info: Found design unit 1: ram_da-SYN
    Info: Found entity 1: ram_da
Info: Found 2 design units, including 1 entities, in source file tri_s11.vhd
    Info: Found design unit 1: tri_s11-bhv
    Info: Found entity 1: tri_s11
Info: Found 2 design units, including 1 entities, in source file tri_s11_1.vhd
    Info: Found design unit 1: tri_s11_1-bhv
    Info: Found entity 1: tri_s11_1
Info: Found 2 design units, including 1 entities, in source file tri_s8.vhd
    Info: Found design unit 1: tri_s8-bhv
    Info: Found entity 1: tri_s8
Info: Found 2 design units, including 1 entities, in source file tri_s8_1.vhd
    Info: Found design unit 1: tri_s8_1-bhv
    Info: Found entity 1: tri_s8_1
Info: Elaborating entity "tri_s8_1" for the top level hierarchy
Info: Implemented 17 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 8 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 142 megabytes of memory during processing
    Info: Processing ended: Thu Oct 04 17:12:22 2007
    Info: Elapsed time: 00:00:04