tri_s11.vhd

来自「双口RAM与PXI总线接口设计」· VHDL 代码 · 共 15 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tri_s11 IS
port ( enaddr2 :IN STD_LOGIC;
	iaddr365 : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	oaddr365 : OUT STD_LOGIC_VECTOR(10 DOWNTO 0));
END  tri_s11;
ARCHITECTURE bhv OF tri_s11 IS
BEGIN
PROCESS(enaddr2,iaddr365)
BEGIN
IF enaddr2 = '1' THEN oaddr365 <= iaddr365 ;
ELSE oaddr365 <="ZZZZZZZZZZZ" ; END IF ;
END PROCESS;
END bhv;