alarm.syr

XLINX做的数字钟

#      AND3                        : 4
#      AND4                        : 4
#      AND4b2                      : 7
#      AND4b3                      : 2
#      AND5b2                      : 1
#      GND                         : 1
#      INV                         : 4
#      MUXCY                       : 1
#      MUXCY_L                     : 3
#      OR2                         : 6
#      VCC                         : 1
#      XOR2                        : 28
# FlipFlops/Latches                : 16
#      FDCE                        : 16
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 20
#      IBUF                        : 18
#      OBUF                        : 2
# Others                           : 4
#      FMAP                        : 4
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v100pq240-4 

 Number of Slices:                      10  out of   1200     0%  
 Number of Slice Flip Flops:            16  out of   2400     0%  
 Number of bonded IOBs:                 22  out of    170    12%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
INPUTM                             | BUFGP                  | 8     |
INPUTH                             | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.478ns (Maximum Frequency: 95.438MHz)
   Minimum input arrival time before clock: 4.357ns
   Maximum output required time after clock: 14.318ns
   Maximum combinational path delay: 12.925ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'INPUTM'
  Clock period: 10.478ns (frequency: 95.438MHz)
  Total number of paths / destination ports: 42 / 12
-------------------------------------------------------------------------
Delay:               10.478ns (Levels of Logic = 3)
  Source:            XLXI_1/XLXI_1/I_Q0 (FF)
  Destination:       XLXI_1/XLXI_1/I_Q3 (FF)
  Source Clock:      INPUTM rising
  Destination Clock: INPUTM rising

  Data Path: XLXI_1/XLXI_1/I_Q0 to XLXI_1/XLXI_1/I_Q3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             9   1.372   2.332  I_Q0 (Q0)
     AND3:I1->O            1   0.738   1.265  I_36_70 (A03B)
     OR2:I1->O             1   0.738   1.265  I_36_75 (OX3)
     XOR2:I1->O            1   0.738   1.265  I_36_73 (D3)
     FDCE:D                    0.765          I_Q3
    ----------------------------------------
    Total                     10.478ns (4.351ns logic, 6.127ns route)
                                       (41.5% logic, 58.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'INPUTH'
  Clock period: 10.478ns (frequency: 95.438MHz)
  Total number of paths / destination ports: 42 / 12
-------------------------------------------------------------------------
Delay:               10.478ns (Levels of Logic = 3)
  Source:            XLXI_2/XLXI_2/I_Q0 (FF)
  Destination:       XLXI_2/XLXI_2/I_Q3 (FF)
  Source Clock:      INPUTH rising
  Destination Clock: INPUTH rising

  Data Path: XLXI_2/XLXI_2/I_Q0 to XLXI_2/XLXI_2/I_Q3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             9   1.372   2.332  I_Q0 (Q0)
     AND3:I1->O            1   0.738   1.265  I_36_70 (A03B)
     OR2:I1->O             1   0.738   1.265  I_36_75 (OX3)
     XOR2:I1->O            1   0.738   1.265  I_36_73 (D3)
     FDCE:D                    0.765          I_Q3
    ----------------------------------------
    Total                     10.478ns (4.351ns logic, 6.127ns route)
                                       (41.5% logic, 58.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'INPUTM'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              4.357ns (Levels of Logic = 2)
  Source:            SET1 (PAD)
  Destination:       XLXI_1/XLXI_2/I_Q0 (FF)
  Destination Clock: INPUTM rising

  Data Path: SET1 to XLXI_1/XLXI_2/I_Q0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   0.989   2.420  SET1_IBUF (SET1_IBUF)
     begin scope: 'XLXI_1/XLXI_2'
     FDCE:CE                   0.948          I_Q0
    ----------------------------------------
    Total                      4.357ns (1.937ns logic, 2.420ns route)
                                       (44.5% logic, 55.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'INPUTH'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              4.357ns (Levels of Logic = 2)
  Source:            SET1 (PAD)
  Destination:       XLXI_2/XLXI_2/I_Q0 (FF)
  Destination Clock: INPUTH rising

  Data Path: SET1 to XLXI_2/XLXI_2/I_Q0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   0.989   2.420  SET1_IBUF (SET1_IBUF)
     begin scope: 'XLXI_2/XLXI_2'
     FDCE:CE                   0.948          I_Q0
    ----------------------------------------
    Total                      4.357ns (1.937ns logic, 2.420ns route)
                                       (44.5% logic, 55.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'INPUTM'
  Total number of paths / destination ports: 16 / 2
-------------------------------------------------------------------------
Offset:              14.318ns (Levels of Logic = 8)
  Source:            XLXI_1/XLXI_1/I_Q0 (FF)
  Destination:       ALARMOUT (PAD)
  Source Clock:      INPUTM rising

  Data Path: XLXI_1/XLXI_1/I_Q0 to ALARMOUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             9   1.372   2.332  I_Q0 (Q0)
     end scope: 'XLXI_1/XLXI_1'
     XOR2:I1->O            1   0.738   1.265  XLXI_19 (MHO0)
     begin scope: 'XLXI_30'
     AND4:I3->O            1   0.738   0.000  I_36_127 (S1)
     MUXCY_L:S->LO         1   0.842   0.000  I_36_129 (C1)
     MUXCY_L:CI->LO        1   0.057   0.000  I_36_147 (C2)
     MUXCY:CI->O           1   0.057   1.265  I_36_165 (O)
     end scope: 'XLXI_30'
     OBUF:I->O                 5.652          ALARMOUT_OBUF (ALARMOUT)
    ----------------------------------------
    Total                     14.318ns (9.456ns logic, 4.862ns route)
                                       (66.0% logic, 34.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'INPUTH'
  Total number of paths / destination ports: 8 / 1
-------------------------------------------------------------------------
Offset:              14.261ns (Levels of Logic = 7)
  Source:            XLXI_2/XLXI_2/I_Q0 (FF)
  Destination:       ALARMOUT (PAD)
  Source Clock:      INPUTH rising

  Data Path: XLXI_2/XLXI_2/I_Q0 to ALARMOUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             9   1.372   2.332  I_Q0 (Q0)
     end scope: 'XLXI_2/XLXI_2'
     XOR2:I1->O            1   0.738   1.265  XLXI_9 (HLO0)
     begin scope: 'XLXI_30'
     AND4:I3->O            1   0.738   0.000  I_36_151 (S2)
     MUXCY_L:S->LO         1   0.842   0.000  I_36_147 (C2)
     MUXCY:CI->O           1   0.057   1.265  I_36_165 (O)
     end scope: 'XLXI_30'
     OBUF:I->O                 5.652          ALARMOUT_OBUF (ALARMOUT)
    ----------------------------------------
    Total                     14.261ns (9.399ns logic, 4.862ns route)
                                       (65.9% logic, 34.1% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 16 / 1
-------------------------------------------------------------------------
Delay:               12.925ns (Levels of Logic = 9)
  Source:            MLI3 (PAD)
  Destination:       ALARMOUT (PAD)

  Data Path: MLI3 to ALARMOUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.989   1.265  MLI3_IBUF (MLI3_IBUF)
     XOR2:I0->O            1   0.738   1.265  XLXI_20 (MLO3)
     begin scope: 'XLXI_30'
     AND4:I0->O            1   0.738   0.000  I_36_110 (S0)
     MUXCY_L:S->LO         1   0.842   0.000  I_36_2 (C0)
     MUXCY_L:CI->LO        1   0.057   0.000  I_36_129 (C1)
     MUXCY_L:CI->LO        1   0.057   0.000  I_36_147 (C2)
     MUXCY:CI->O           1   0.057   1.265  I_36_165 (O)
     end scope: 'XLXI_30'
     OBUF:I->O                 5.652          ALARMOUT_OBUF (ALARMOUT)
    ----------------------------------------
    Total                     12.925ns (9.130ns logic, 3.795ns route)
                                       (70.6% logic, 29.4% route)

=========================================================================
CPU : 3.45 / 3.73 s | Elapsed : 3.00 / 4.00 s
 
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Total memory usage is 86668 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    8 (   0 filtered)
Number of infos    :    0 (   0 filtered)