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* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : v100pq240-4 Number of Slices: 22 out of 1200 1% Number of Slice Flip Flops: 40 out of 2400 1% Number of bonded IOBs: 34 out of 170 20% Number of GCLKs: 3 out of 4 75% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+----------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+----------------------------+-------+ALMSETH | BUFGP | 8 |CLOCK1(XLXI_8:O) | BUFG(*)(XLXI_2/XLXI_2/I_Q1)| 24 |ALMSETM | BUFGP | 8 |-----------------------------------+----------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -4 Minimum period: 14.215ns (Maximum Frequency: 70.348MHz) Minimum input arrival time before clock: 5.854ns Maximum output required time after clock: 14.406ns Maximum combinational path delay: No path found=========================================================================
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\文档\桌面\数字钟/_ngo -uc CLOCK.ucf-p xcv100-pq240-4 CLOCK.ngc CLOCK.ngd Reading NGO file 'D:/文档/桌面/数字钟/CLOCK.ngc' ...Applying constraints in "CLOCK.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "CLOCK.ngd" ...Writing NGDBUILD log file "CLOCK.bld"...NGDBUILD done.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "D:/文档/桌面/数字钟/Plus60.vhf" in Library work.Architecture behavioral of Entity cd4ce_mxilinx_plus60 is up to date.Architecture behavioral of Entity plus60 is up to date.Compiling vhdl file "D:/文档/桌面/数字钟/Hour.vhf" in Library work.Architecture behavioral of Entity cd4ce_mxilinx_hour is up to date.Architecture behavioral of Entity hour is up to date.Compiling vhdl file "D:/文档/桌面/数字钟/alarm.vhf" in Library work.Architecture behavioral of Entity and16_mxilinx_alarm is up to date.Architecture behavioral of Entity alarm is up to date.Compiling vhdl file "D:/文档/桌面/数字钟/CLOCK.vhf" in Library work.Architecture behavioral of Entity clock is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <CLOCK> (Architecture <behavioral>).WARNING:Xst:753 - "D:/文档/桌面/数字钟/CLOCK.vhf" line 238: Unconnected output port 'OUTPUT59' of component 'alarm'.Entity <CLOCK> analyzed. Unit <CLOCK> generated.Analyzing Entity <Plus60> (Architecture <behavioral>).WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 305: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Plus60'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 305: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Plus60'. Set user-defined property "HU_SET = XLXI_1_0" for instance <XLXI_1> in unit <Plus60>.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 316: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Plus60'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 316: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Plus60'. Set user-defined property "HU_SET = XLXI_2_1" for instance <XLXI_2> in unit <Plus60>.Entity <Plus60> analyzed. Unit <Plus60> generated.Analyzing Entity <CD4CE_MXILINX_Plus60> (Architecture <behavioral>). Set user-defined property "INIT = 0" for instance <I_Q0> in unit <CD4CE_MXILINX_Plus60>. Set user-defined property "INIT = 0" for instance <I_Q1> in unit <CD4CE_MXILINX_Plus60>. Set user-defined property "INIT = 0" for instance <I_Q2> in unit <CD4CE_MXILINX_Plus60>. Set user-defined property "INIT = 0" for instance <I_Q3> in unit <CD4CE_MXILINX_Plus60>.Entity <CD4CE_MXILINX_Plus60> analyzed. Unit <CD4CE_MXILINX_Plus60> generated.Analyzing Entity <Hour> (Architecture <behavioral>).WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 312: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Hour'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 312: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Hour'. Set user-defined property "HU_SET = XLXI_1_0" for instance <XLXI_1> in unit <Hour>.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 323: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Hour'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 323: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Hour'. Set user-defined property "HU_SET = XLXI_2_1" for instance <XLXI_2> in unit <Hour>.Entity <Hour> analyzed. Unit <Hour> generated.Analyzing Entity <CD4CE_MXILINX_Hour> (Architecture <behavioral>). Set user-defined property "INIT = 0" for instance <I_Q0> in unit <CD4CE_MXILINX_Hour>. Set user-defined property "INIT = 0" for instance <I_Q1> in unit <CD4CE_MXILINX_Hour>. Set user-defined property "INIT = 0" for instance <I_Q2> in unit <CD4CE_MXILINX_Hour>. Set user-defined property "INIT = 0" for instance <I_Q3> in unit <CD4CE_MXILINX_Hour>.Entity <CD4CE_MXILINX_Hour> analyzed. Unit <CD4CE_MXILINX_Hour> generated.Analyzing Entity <alarm> (Architecture <behavioral>). Set user-defined property "HU_SET = XLXI_30_0" for instance <XLXI_30> in unit <alarm>.Entity <alarm> analyzed. Unit <alarm> generated.Analyzing Entity <AND16_MXILINX_alarm> (Architecture <behavioral>). Set user-defined property "RLOC = R1C0.S1" for instance <I_36_2> in unit <AND16_MXILINX_alarm>. Set user-defined property "RLOC = R1C0.S1" for instance <I_36_29> in unit <AND16_MXILINX_alarm>. Set user-defined property "RLOC = R1C0.S1" for instance <I_36_129> in unit <AND16_MXILINX_alarm>. Set user-defined property "RLOC = R1C0.S1" for instance <I_36_138> in unit <AND16_MXILINX_alarm>. Set user-defined property "RLOC = R0C0.S1" for instance <I_36_142> in unit <AND16_MXILINX_alarm>. Set user-defined property "RLOC = R0C0.S1" for instance <I_36_147> in unit <AND16_MXILINX_alarm>. Set user-defined property "RLOC = R0C0.S1" for instance <I_36_165> in unit <AND16_MXILINX_alarm>. Set user-defined property "RLOC = R0C0.S1" for instance <I_36_170> in unit <AND16_MXILINX_alarm>.Entity <AND16_MXILINX_alarm> analyzed. Unit <AND16_MXILINX_alarm> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <AND16_MXILINX_alarm>. Related source file is "D:/文档/桌面/数字钟/alarm.vhf".Unit <AND16_MXILINX_alarm> synthesized.Synthesizing Unit <CD4CE_MXILINX_Hour>. Related source file is "D:/文档/桌面/数字钟/Hour.vhf".Unit <CD4CE_MXILINX_Hour> synthesized.Synthesizing Unit <CD4CE_MXILINX_Plus60>. Related source file is "D:/文档/桌面/数字钟/Plus60.vhf".Unit <CD4CE_MXILINX_Plus60> synthesized.Synthesizing Unit <alarm>. Related source file is "D:/文档/桌面/数字钟/alarm.vhf".Unit <alarm> synthesized.Synthesizing Unit <Hour>. Related source file is "D:/文档/桌面/数字钟/Hour.vhf".Unit <Hour> synthesized.Synthesizing Unit <Plus60>. Related source file is "D:/文档/桌面/数字钟/Plus60.vhf".Unit <Plus60> synthesized.Synthesizing Unit <CLOCK>. Related source file is "D:/文档/桌面/数字钟/CLOCK.vhf".Unit <CLOCK> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <CLOCK> ...Optimizing unit <CD4CE_MXILINX_Plus60> ...Optimizing unit <CD4CE_MXILINX_Hour> ...Optimizing unit <AND16_MXILINX_alarm> ...Loading device for application Rf_Device from file 'v100.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block CLOCK, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : v100pq240-4 Number of Slices: 22 out of 1200 1% Number of Slice Flip Flops: 40 out of 2400 1% Number of bonded IOBs: 34 out of 170 20% Number of GCLKs: 3 out of 4 75% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+----------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+----------------------------+-------+ALMSETH | BUFGP | 8 |CLOCK1(XLXI_8:O) | BUFG(*)(XLXI_2/XLXI_2/I_Q0)| 24 |ALMSETM | BUFGP | 8 |-----------------------------------+----------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -4 Minimum period: 14.215ns (Maximum Frequency: 70.348MHz) Minimum input arrival time before clock: 5.854ns Maximum output required time after clock: 14.406ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Post-Synthesis Simulation Model".INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM simulation primitives and has to be used with UNISIM library for correct compilation and simulation.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\文档\桌面\数字钟/_ngo -uc CLOCK.ucf-p xcv100-pq240-4 CLOCK.ngc CLOCK.ngd Reading NGO file 'D:/文档/桌面/数字钟/CLOCK.ngc' ...Applying constraints in "CLOCK.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "CLOCK.ngd" ...Writing NGDBUILD log file "CLOCK.bld"...NGDBUILD done.
Started process "Map".Using target part "v100pq240-4".Mapping design into LUTs...ERROR:MapLib:93 - Illegal LOC on IPAD symbol "ALMSETH" or BUFGP symbol "ALMSETH_BUFGP" (output signal=ALMSETH_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.ERROR:MapLib:93 - Illegal LOC on IPAD symbol "ALMSETM" or BUFGP symbol "ALMSETM_BUFGP" (output signal=ALMSETM_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.Error found in mapping process, exiting...Errors found during the mapping phase. Please see map report file f⌨️ 快捷键说明
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