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Selected Device : v100pq240-4 Number of Slices: 12 out of 1200 1% Number of Slice Flip Flops: 24 out of 2400 1% Number of bonded IOBs: 29 out of 170 17% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+CLOCK | BUFGP | 24 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: 10.478ns (Maximum Frequency: 95.438MHz) Minimum input arrival time before clock: 3.851ns Maximum output required time after clock: 14.825ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "View HDL Functional Model".DRC Check completed: No Error found.Vhdl netlist file generated.
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "D:/文档/桌面/数字钟/Plus60.vhf" in Library work.Architecture behavioral of Entity cd4ce_mxilinx_plus60 is up to date.Architecture behavioral of Entity plus60 is up to date.Compiling vhdl file "D:/文档/桌面/数字钟/Hour.vhf" in Library work.Architecture behavioral of Entity cd4ce_mxilinx_hour is up to date.Architecture behavioral of Entity hour is up to date.Compiling vhdl file "D:/文档/桌面/数字钟/CLOCK.vhf" in Library work.Entity <clock> compiled.Entity <clock> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <CLOCK> (Architecture <behavioral>).Entity <CLOCK> analyzed. Unit <CLOCK> generated.Analyzing Entity <Plus60> (Architecture <behavioral>).WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 305: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Plus60'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 305: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Plus60'. Set user-defined property "HU_SET = XLXI_1_0" for instance <XLXI_1> in unit <Plus60>.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 316: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Plus60'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 316: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Plus60'. Set user-defined property "HU_SET = XLXI_2_1" for instance <XLXI_2> in unit <Plus60>.Entity <Plus60> analyzed. Unit <Plus60> generated.Analyzing Entity <CD4CE_MXILINX_Plus60> (Architecture <behavioral>). Set user-defined property "INIT = 0" for instance <I_Q0> in unit <CD4CE_MXILINX_Plus60>. Set user-defined property "INIT = 0" for instance <I_Q1> in unit <CD4CE_MXILINX_Plus60>. Set user-defined property "INIT = 0" for instance <I_Q2> in unit <CD4CE_MXILINX_Plus60>. Set user-defined property "INIT = 0" for instance <I_Q3> in unit <CD4CE_MXILINX_Plus60>.Entity <CD4CE_MXILINX_Plus60> analyzed. Unit <CD4CE_MXILINX_Plus60> generated.Analyzing Entity <Hour> (Architecture <behavioral>).WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 312: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Hour'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 312: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Hour'. Set user-defined property "HU_SET = XLXI_1_0" for instance <XLXI_1> in unit <Hour>.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 323: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Hour'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 323: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Hour'. Set user-defined property "HU_SET = XLXI_2_1" for instance <XLXI_2> in unit <Hour>.Entity <Hour> analyzed. Unit <Hour> generated.Analyzing Entity <CD4CE_MXILINX_Hour> (Architecture <behavioral>). Set user-defined property "INIT = 0" for instance <I_Q0> in unit <CD4CE_MXILINX_Hour>. Set user-defined property "INIT = 0" for instance <I_Q1> in unit <CD4CE_MXILINX_Hour>. Set user-defined property "INIT = 0" for instance <I_Q2> in unit <CD4CE_MXILINX_Hour>. Set user-defined property "INIT = 0" for instance <I_Q3> in unit <CD4CE_MXILINX_Hour>.Entity <CD4CE_MXILINX_Hour> analyzed. Unit <CD4CE_MXILINX_Hour> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <CD4CE_MXILINX_Hour>. Related source file is "D:/文档/桌面/数字钟/Hour.vhf".Unit <CD4CE_MXILINX_Hour> synthesized.Synthesizing Unit <CD4CE_MXILINX_Plus60>. Related source file is "D:/文档/桌面/数字钟/Plus60.vhf".Unit <CD4CE_MXILINX_Plus60> synthesized.Synthesizing Unit <Hour>. Related source file is "D:/文档/桌面/数字钟/Hour.vhf".Unit <Hour> synthesized.Synthesizing Unit <Plus60>. Related source file is "D:/文档/桌面/数字钟/Plus60.vhf".Unit <Plus60> synthesized.Synthesizing Unit <CLOCK>. Related source file is "D:/文档/桌面/数字钟/CLOCK.vhf".Unit <CLOCK> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <CLOCK> ...Optimizing unit <CD4CE_MXILINX_Plus60> ...Optimizing unit <CD4CE_MXILINX_Hour> ...Loading device for application Rf_Device from file 'v100.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block CLOCK, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : v100pq240-4 Number of Slices: 12 out of 1200 1% Number of Slice Flip Flops: 24 out of 2400 1% Number of bonded IOBs: 31 out of 170 18% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+CLOCK | BUFGP | 24 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: 14.369ns (Maximum Frequency: 69.594MHz) Minimum input arrival time before clock: 5.854ns Maximum output required time after clock: 14.418ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "View HDL Functional Model".DRC Check completed: No Error found.Vhdl netlist file generated.
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "D:/文档/桌面/数字钟/Plus60.vhf" in Library work.Architecture behavioral of Entity cd4ce_mxilinx_plus60 is up to date.Architecture behavioral of Entity plus60 is up to date.Compiling vhdl file "D:/文档/桌面/数字钟/Hour.vhf" in Library work.Architecture behavioral of Entity cd4ce_mxilinx_hour is up to date.Architecture behavioral of Entity hour is up to date.Compiling vhdl file "D:/文档/桌面/数字钟/CLOCK.vhf" in Library work.Entity <clock> compiled.Entity <clock> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <CLOCK> (Architecture <behavioral>).Entity <CLOCK> analyzed. Unit <CLOCK> generated.Analyzing Entity <Plus60> (Architecture <behavioral>).WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 305: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Plus60'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 305: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Plus60'. Set user-defined property "HU_SET = XLXI_1_0" for instance <XLXI_1> in unit <Plus60>.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 316: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Plus60'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 316: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Plus60'. Set user-defined property "HU_SET = XLXI_2_1" for instance <XLXI_2> in unit <Plus60>.Entity <Plus60> analyzed. Unit <Plus60> generated.Analyzing Entity <CD4CE_MXILINX_Plus60> (Architecture <behavioral>). Set user-defined property "INIT = 0" for instance <I_Q0> in unit <CD4CE_MXILINX_Plus60>. Set user-defined property "INIT = 0" for instance <I_Q1> in unit <CD4CE_MXILINX_Plus60>. Set user-defined property "INIT = 0" for instance <I_Q2> in unit <CD4CE_MXILINX_Plus60>. Set user-defined property "INIT = 0" for instance <I_Q3> in unit <CD4CE_MXILINX_Plus60>.Entity <CD4CE_MXILINX_Plus60> analyzed. Unit <CD4CE_MXILINX_Plus60> generated.Analyzing Entity <Hour> (Architecture <behavioral>).WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 312: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Hour'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 312: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Hour'. Set user-defined property "HU_SET = XLXI_1_0" for instance <XLXI_1> in unit <Hour>.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 323: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Hour'.WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 323: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Hour'. Set user-defined property "HU_SET = XLXI_2_1" for instance <XLXI_2> in unit <Hour>.Entity <Hour> analyzed. Unit <Hour> generated.Analyzing Entity <CD4CE_MXILINX_Hour> (Architecture <behavioral>). Set user-defined property "INIT = 0" for instance <I_Q0> in unit <CD4CE_MXILINX_Hour>. Set user-defined property "INIT = 0" for instance <I_Q1> in unit <CD4CE_MXILINX_Hour>. Set user-defined property "INIT = 0" for instance <I_Q2> in unit <CD4CE_MXILINX_Hour>. Set user-defined property "INIT = 0" for instance <I_Q3> in unit <CD4CE_MXILINX_Hour>.Entity <CD4CE_MXILINX_Hour> analyzed. Unit <CD4CE_MXILINX_Hour> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <CD4CE_MXILINX_Hour>. Related source file is "D:/文档/桌面/数字钟/Hour.vhf".Unit <CD4CE_MXILINX_Hour> synthesized.Synthesizing Unit <CD4CE_MXILINX_Plus60>. Related source file is "D:/文档/桌面/数字钟/Plus60.vhf".Unit <CD4CE_MXILINX_Plus60> synthesized.Synthesizing Unit <Hour>. Related source file is "D:/文档/桌面/数字钟/Hour.vhf".Unit <Hour> synthesized.Synthesizing Unit <Plus60>. Related source file is "D:/文档/桌面/数字钟/Plus60.vhf".Unit <Plus60> synthesized.Synthesizing Unit <CLOCK>. Related source file is "D:/文档/桌面/数字钟/CLOCK.vhf".Unit <CLOCK> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <CLOCK> ...⌨️ 快捷键说明
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