__projnav.log

XLINX做的数字钟

Project Navigator Auto-Make Log File
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Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.


Project Navigator Auto-Make Log File
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Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.


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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.


Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.








Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.


Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.


Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.




Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/文档/桌面/数字钟/Plus60.vhf" in Library work.
Entity <CD4CE_MXILINX_Plus60> compiled.
Entity <CD4CE_MXILINX_Plus60> (Architecture <BEHAVIORAL>) compiled.
Entity <Plus60> compiled.
Entity <Plus60> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file "D:/文档/桌面/数字钟/Hour.vhf" in Library work.
Entity <CD4CE_MXILINX_Hour> compiled.
Entity <CD4CE_MXILINX_Hour> (Architecture <BEHAVIORAL>) compiled.
Entity <Hour> compiled.
Entity <Hour> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file "D:/文档/桌面/数字钟/CLOCK.vhf" in Library work.
Entity <CLOCK> compiled.
Entity <CLOCK> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <CLOCK> (Architecture <BEHAVIORAL>).
Entity <CLOCK> analyzed. Unit <CLOCK> generated.

Analyzing Entity <Plus60> (Architecture <behavioral>).
WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 305: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Plus60'.
WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 305: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Plus60'.
    Set user-defined property "HU_SET =  XLXI_1_0" for instance <XLXI_1> in unit <Plus60>.
WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 316: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Plus60'.
WARNING:Xst:753 - "D:/文档/桌面/数字钟/Plus60.vhf" line 316: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Plus60'.
    Set user-defined property "HU_SET =  XLXI_2_1" for instance <XLXI_2> in unit <Plus60>.
Entity <Plus60> analyzed. Unit <Plus60> generated.

Analyzing Entity <CD4CE_MXILINX_Plus60> (Architecture <behavioral>).
    Set user-defined property "INIT =  0" for instance <I_Q0> in unit <CD4CE_MXILINX_Plus60>.
    Set user-defined property "INIT =  0" for instance <I_Q1> in unit <CD4CE_MXILINX_Plus60>.
    Set user-defined property "INIT =  0" for instance <I_Q2> in unit <CD4CE_MXILINX_Plus60>.
    Set user-defined property "INIT =  0" for instance <I_Q3> in unit <CD4CE_MXILINX_Plus60>.
Entity <CD4CE_MXILINX_Plus60> analyzed. Unit <CD4CE_MXILINX_Plus60> generated.

Analyzing Entity <Hour> (Architecture <behavioral>).
WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 312: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Hour'.
WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 312: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Hour'.
    Set user-defined property "HU_SET =  XLXI_1_0" for instance <XLXI_1> in unit <Hour>.
WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 323: Unconnected output port 'CEO' of component 'CD4CE_MXILINX_Hour'.
WARNING:Xst:753 - "D:/文档/桌面/数字钟/Hour.vhf" line 323: Unconnected output port 'TC' of component 'CD4CE_MXILINX_Hour'.
    Set user-defined property "HU_SET =  XLXI_2_1" for instance <XLXI_2> in unit <Hour>.
Entity <Hour> analyzed. Unit <Hour> generated.

Analyzing Entity <CD4CE_MXILINX_Hour> (Architecture <behavioral>).
    Set user-defined property "INIT =  0" for instance <I_Q0> in unit <CD4CE_MXILINX_Hour>.
    Set user-defined property "INIT =  0" for instance <I_Q1> in unit <CD4CE_MXILINX_Hour>.
    Set user-defined property "INIT =  0" for instance <I_Q2> in unit <CD4CE_MXILINX_Hour>.
    Set user-defined property "INIT =  0" for instance <I_Q3> in unit <CD4CE_MXILINX_Hour>.
Entity <CD4CE_MXILINX_Hour> analyzed. Unit <CD4CE_MXILINX_Hour> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <CD4CE_MXILINX_Hour>.
    Related source file is "D:/文档/桌面/数字钟/Hour.vhf".
Unit <CD4CE_MXILINX_Hour> synthesized.


Synthesizing Unit <CD4CE_MXILINX_Plus60>.
    Related source file is "D:/文档/桌面/数字钟/Plus60.vhf".
Unit <CD4CE_MXILINX_Plus60> synthesized.


Synthesizing Unit <Hour>.
    Related source file is "D:/文档/桌面/数字钟/Hour.vhf".
Unit <Hour> synthesized.


Synthesizing Unit <Plus60>.
    Related source file is "D:/文档/桌面/数字钟/Plus60.vhf".
Unit <Plus60> synthesized.


Synthesizing Unit <CLOCK>.
    Related source file is "D:/文档/桌面/数字钟/CLOCK.vhf".
Unit <CLOCK> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <CLOCK> ...

Optimizing unit <CD4CE_MXILINX_Plus60> ...

Optimizing unit <CD4CE_MXILINX_Hour> ...
Loading device for application Rf_Device from file 'v100.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block CLOCK, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
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