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# Schematic : PDCL (jhdparse)
__projnav/Plus60_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/Plus60_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
Plus60.vhf
Plus60.cmd_log
# Bencher : Creating project file
TEST60_bencher.prj
# ProjNav -> New Source -> TBW
TEST60.vhw
TEST60.ano
TEST60.tfw
TEST60.ant
# Schematic : PDCL (jhdparse)
__projnav/Plus60_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
Plus60.vhf
Plus60.cmd_log
# Bencher : Creating project file
TEST60_bencher.prj
# ProjNav -> New Source -> TBW
TEST60.vhw
TEST60.ano
TEST60.tfw
TEST60.ant
# ModelSim : Launch ModelSim Simulator
Plus60.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# Bencher : Creating project file
TEST60_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
TEST60_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
TEST60.vhw
TEST60.ano
TEST60.tfw
TEST60.ant
# ModelSim : Simulate Behavioral VHDL Model
TEST60.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Schematic : PDCL (jhdparse)
__projnav/Plus60_jhdparse_tcl.rsp
# Bencher : Creating project file
TEST60_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# xst flow : RunXST
Plus60_summary.html
# Schematic : PDCL (jhdparse)
__projnav/Plus60_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
Plus60.vhf
Plus60.cmd_log
# Bencher : Creating project file
TEST60_bencher.prj
# Bencher : Creating project file
TEST60_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
TEST60_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
TEST60.vhw
TEST60.ano
TEST60.tfw
TEST60.ant
# ModelSim : Simulate Behavioral VHDL Model
test60.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
test60_bencher.prj
# ProjNav -> New Source -> TBW
test60.vhw
test60.ano
test60.tfw
test60.ant
# Bencher : Creating project file
test60_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test60_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
__projnav/Plus60_jhdparse_tcl.rsp
# Bencher : Creating project file
test60_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# xst flow : RunXST
Plus60_summary.html
# Bencher : Creating project file
test601_bencher.prj
# ProjNav -> New Source -> TBW
test601.vhw
test601.ano
test601.tfw
test601.ant
# Bencher : Creating project file
test601_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test601_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test601_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test601.vhw
test601.ano
test601.tfw
test601.ant
# ModelSim : Simulate Behavioral VHDL Model
test601.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
test601_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
test601.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
test601_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test601_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test601_bencher.prj
# ModelSim : Simulate Behavioral VHDL Model
test601.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
test601_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# xst flow : RunXST
Plus60_summary.html
# Schematic : PDCL (jhdparse)
__projnav/Plus60_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
Plus60.vhf
Plus60.cmd_log
# Bencher : Creating project file
TEST602_bencher.prj
# ProjNav -> New Source -> TBW
TEST602.vhw
TEST602.ano
TEST602.tfw
TEST602.ant
# Bencher : Creating project file
TEST602_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
__projnav/Plus60_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
Plus60.vhf
Plus60.cmd_log
# Bencher : Creating project file
TEST602_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
TEST602.vhw
TEST602.ano
TEST602.tfw
TEST602.ant
# ModelSim : Simulate Behavioral VHDL Model
TEST602.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Schematic : PDCL (jhdparse)
__projnav/Plus60_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/Hour_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
Hour.vhf
Hour.cmd_log
# Bencher : Creating project file
TEST241_bencher.prj
# ProjNav -> New Source -> TBW
TEST241.vhw
TEST241.ano
TEST241.tfw
TEST241.ant
# Bencher : Creating project file
TEST241_bencher.prj
# ProjNav -> New Source -> TBW
TEST241.vhw
TEST241.ano
TEST241.tfw
TEST241.ant
# Schematic : PDCL (jhdparse)
__projnav/Hour_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
Hour.vhf
Hour.cmd_log
# Bencher : Creating project file
TEST241_bencher.prj
# ProjNav -> New Source -> TBW
TEST241.vhw
TEST241.ano
TEST241.tfw
TEST241.ant
# Bencher : Creating project file
TEST241_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
TEST241_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
TEST241.vhw
TEST241.ano
TEST241.tfw
TEST241.ant
# ModelSim : Simulate Behavioral VHDL Model
TEST241.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Schematic : PDCL (jhdparse)
__projnav/Hour_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/Hour_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/Hour_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/Hour_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/Hour_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/Hour_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
Hour.vhf
Hour.cmd_log
# Bencher : Creating project file
TEST242_bencher.prj
# ProjNav -> New Source -> TBW
TEST242.vhw
TEST242.ano
TEST242.tfw
TEST242.ant
# Bencher : Creating project file
TEST242_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
TEST242_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
TEST242.vhw
TEST242.ano
TEST242.tfw
TEST242.ant
# ModelSim : Simulate Behavioral VHDL Model
TEST242.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Schematic : PDCL (jhdparse)
__projnav/CLOCK_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/CLOCK_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/CLOCK_jhdparse_tcl.rsp
# xst flow : RunXST
CLOCK_summary.html
# Schematic : View HDL Functional Model
CLOCK.vhf
CLOCK.cmd_log
# Schematic : View HDL Functional Model
Plus60.vhf
Plus60.cmd_log
# XST (Creating Lso File) : 
CLOCK.lso
# xst flow : RunXST
CLOCK_summary.html
# xst flow : RunXST
CLOCK.syr
CLOCK.prj
CLOCK.sprj
CLOCK.ana
CLOCK.stx
CLOCK.cmd_log
CLOCK.ngc
CLOCK.ngr
# Schematic : PDCL (jhdparse)
__projnav/CLOCK_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
CLOCK.vhf
CLOCK.cmd_log
# XST (Creating Lso File) : 
CLOCK.lso
# xst flow : RunXST
CLOCK_summary.html
# xst flow : RunXST
CLOCK.syr
CLOCK.prj
CLOCK.sprj
CLOCK.ana
CLOCK.stx
CLOCK.cmd_log
CLOCK.ngc
CLOCK.ngr
# Bencher : Creating project file
TEST241_bencher.prj
# Bencher : Creating project file
TEST242_bencher.prj
# Schematic : PDCL (jhdparse)
__projnav/alarm_jhdparse_tcl.rsp
# xst flow : RunXST
alarm_summary.html
# Schematic : PDCL (jhdparse)
__projnav/CLOCK_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
CLOCK.vhf
CLOCK.cmd_log
# XST (Creating Lso File) : 
CLOCK.lso
# xst flow : RunXST
CLOCK_summary.html
# xst flow : RunXST
CLOCK.syr
CLOCK.prj
CLOCK.sprj
CLOCK.ana
CLOCK.stx
CLOCK.cmd_log
CLOCK.ngc
CLOCK.ngr
# Schematic : PDCL (jhdparse)
__projnav/alarm_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/CLOCK_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
alarm.vhf
alarm.cmd_log
# XST (Creating Lso File) : 
alarm.lso
# xst flow : RunXST
alarm_summary.html
# xst flow : RunXST
alarm.syr
alarm.prj
alarm.sprj
alarm.ana
alarm.stx
alarm.cmd_log
alarm.ngc
alarm.ngr
# Implementation : Generate Post-Synthesis Simulation Model
alarm_synthesis.vhd
alarm_synthesis.nlf
alarm.vhdsim_synth
alarm.synth_nlf
alarm.cmd_log
alarm_synthesis.vhd
# Schematic : View HDL Functional Model
CLOCK.vhf
CLOCK.cmd_log
# XST (Creating Lso File) : 
CLOCK.lso
# xst flow : RunXST
CLOCK_summary.html
# xst flow : RunXST
CLOCK.syr
CLOCK.prj
CLOCK.sprj
CLOCK.ana
CLOCK.stx
CLOCK.cmd_log
alarm.ngc
CLOCK.ngc
alarm.ngr
CLOCK.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\???\×???\??×???/_ngo"
CLOCK.ngd
CLOCK_ngdbuild.nav
CLOCK.bld
CLOCK.ucf.untf
CLOCK.cmd_log
# Schematic : PDCL (jhdparse)
__projnav/CLOCK_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
CLOCK.vhf
CLOCK.cmd_log
# XST (Creating Lso File) : 
CLOCK.lso
# xst flow : RunXST
CLOCK_summary.html
# xst flow : RunXST
CLOCK.syr
CLOCK.prj
CLOCK.sprj
CLOCK.ana
CLOCK.stx
CLOCK.cmd_log
alarm.ngc
CLOCK.ngc
alarm.ngr
CLOCK.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\???\×???\??×???/_ngo"
CLOCK.ngd
CLOCK_ngdbuild.nav
CLOCK.bld
CLOCK.ucf.untf
CLOCK.cmd_log
# XST (Creating Lso File) : 
CLOCK.lso
# xst flow : RunXST
CLOCK_summary.html
# xst flow : RunXST
CLOCK.syr
CLOCK.prj
CLOCK.sprj
CLOCK.ana
CLOCK.stx
CLOCK.cmd_log
alarm.ngc
CLOCK.ngc
alarm.ngr
CLOCK.ngr
# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# Assign Package Pins (UCF)
# Implementation : Generate Post-Synthesis Simulation Model
CLOCK_synthesis.vhd
CLOCK_synthesis.nlf
CLOCK.vhdsim_synth
CLOCK.synth_nlf
CLOCK.cmd_log
CLOCK_synthesis.vhd
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\???\×???\??×???/_ngo"
CLOCK.ngd
CLOCK_ngdbuild.nav
CLOCK.bld
CLOCK.ucf.untf
CLOCK.cmd_log
# Implementation : Map
CLOCK_summary.html
# Implementation : Map
CLOCK_map.ncd
CLOCK.ngm
CLOCK.pcf
CLOCK.nc1
CLOCK.mrp
CLOCK_map.mrp
CLOCK.mdf
CLOCK.cmd_log
MAP_NO_GUIDE_FILE_CPF "CLOCK"
CLOCK_map.ngm
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\???\×???\??×???/_ngo"
CLOCK.ngd
CLOCK_ngdbuild.nav
CLOCK.bld
CLOCK.ucf.untf
CLOCK.cmd_log
# Implementation : Map
CLOCK_summary.html
# Implementation : Map
CLOCK_map.ncd
CLOCK.ngm
CLOCK.pcf
CLOCK.nc1
CLOCK.mrp
CLOCK_map.mrp
CLOCK.mdf
CLOCK.cmd_log
MAP_NO_GUIDE_FILE_CPF "CLOCK"
CLOCK_map.ngm
# Schematic : PDCL (jhdparse)
__projnav/alarm_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/CLOCK_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/CLOCK_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
CLOCK.vhf
CLOCK.cmd_log
# Schematic : View HDL Functional Model
alarm.vhf
alarm.cmd_log
# XST (Creating Lso File) : 
CLOCK.lso
# xst flow : RunXST
CLOCK_summary.html
# xst flow : RunXST
CLOCK.syr
CLOCK.prj
CLOCK.sprj
CLOCK.ana
CLOCK.stx
CLOCK.cmd_log
alarm.ngc
CLOCK.ngc
alarm.ngr
CLOCK.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\???\×???\??×???/_ngo"
CLOCK.ngd
CLOCK_ngdbuild.nav
CLOCK.bld
CLOCK.ucf.untf
CLOCK.cmd_log
# XST (Creating Lso File) : 
CLOCK.lso
# xst flow : RunXST
CLOCK_summary.html
# xst flow : RunXST
CLOCK.syr
CLOCK.prj
CLOCK.sprj
CLOCK.ana
CLOCK.stx
CLOCK.cmd_log
alarm.ngc
CLOCK.ngc
alarm.ngr
CLOCK.ngr
# Implementation : Generate Post-Synthesis Simulation Model
CLOCK_synthesis.vhd
CLOCK_synthesis.nlf
CLOCK.vhdsim_synth
CLOCK.synth_nlf
CLOCK.cmd_log
CLOCK_synthesis.vhd
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\???\×???\??×???/_ngo"
CLOCK.ngd
CLOCK_ngdbuild.nav
CLOCK.bld
CLOCK.ucf.untf
CLOCK.cmd_log
# Implementation : Map
CLOCK_summary.html
# Implementation : Map
CLOCK_map.ncd
CLOCK.ngm
CLOCK.pcf
CLOCK.nc1
CLOCK.mrp
CLOCK_map.mrp
CLOCK.mdf
CLOCK.cmd_log
MAP_NO_GUIDE_FILE_CPF "CLOCK"
CLOCK_map.ngm
# Implementation : Map
CLOCK_summary.html
# Implementation : Map
CLOCK_map.ncd
CLOCK.ngm
CLOCK.pcf
CLOCK.nc1
CLOCK.mrp
CLOCK_map.mrp
CLOCK.mdf
CLOCK.cmd_log
MAP_NO_GUIDE_FILE_CPF "CLOCK"
CLOCK_map.ngm
# Schematic : PDCL (jhdparse)
__projnav/alarm_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/CLOCK_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/CLOCK_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
CLOCK.vhf
CLOCK.cmd_log
# Schematic : View HDL Functional Model
alarm.vhf
alarm.cmd_log
# XST (Creating Lso File) : 
CLOCK.lso
# xst flow : RunXST
CLOCK_summary.html
# xst flow : RunXST
CLOCK.syr
CLOCK.prj
CLOCK.sprj
CLOCK.ana
CLOCK.stx
CLOCK.cmd_log
alarm.ngc
CLOCK.ngc
alarm.ngr
CLOCK.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\???\×???\??×???/_ngo"
CLOCK.ngd
CLOCK_ngdbuild.nav
CLOCK.bld
CLOCK.ucf.untf
CLOCK.cmd_log
# Implementation : Generate Post-Synthesis Simulation Model
CLOCK_synthesis.vhd
CLOCK_synthesis.nlf
CLOCK.vhdsim_synth
CLOCK.synth_nlf
CLOCK.cmd_log
CLOCK_synthesis.vhd
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\???\×???\??×???/_ngo"
CLOCK.ngd
CLOCK_ngdbuild.nav
CLOCK.bld
CLOCK.ucf.untf
CLOCK.cmd_log
# Implementation : Map
CLOCK_summary.html
# Implementation : Map
CLOCK_map.ncd
CLOCK.ngm
CLOCK.pcf
CLOCK.nc1
CLOCK.mrp
CLOCK_map.mrp
CLOCK.mdf
CLOCK.cmd_log
MAP_NO_GUIDE_FILE_CPF "CLOCK"
CLOCK_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
CLOCK.twr
CLOCK.twx
CLOCK.tsi
CLOCK.cmd_log
# Implementation : Place & Route
CLOCK_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
CLOCK.ncd
CLOCK.par
CLOCK.pad
CLOCK_pad.txt
CLOCK_pad.csv
CLOCK.pad_txt
CLOCK.dly
reportgen.log
CLOCK.xpi
CLOCK.grf
CLOCK.itr
CLOCK_last_par.ncd
CLOCK.placed_ncd_tracker
CLOCK.routed_ncd_tracker
CLOCK.cmd_log
PAR_NO_GUIDE_FILE_CPF "CLOCK"
# Generate Programming File
__projnav/CLOCK_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
CLOCK.ut
# Generate Programming File
CLOCK.bgn
CLOCK.rbt
CLOCK.ll
CLOCK.msk
CLOCK.drc
CLOCK.nky
CLOCK.bit
CLOCK.bin
CLOCK.isc
CLOCK.cmd_log
123

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