transcript

XLINX做的数字钟

# Reading D:/Modeltech_6.0/tcl/vsim/pref.tcl 
# do testclock1.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package vcomponents
# -- Compiling entity cd4ce_mxilinx_plus60
# -- Compiling architecture behavioral of cd4ce_mxilinx_plus60
# -- Compiling entity plus60
# -- Compiling architecture behavioral of plus60
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package vcomponents
# -- Compiling entity cd4ce_mxilinx_hour
# -- Compiling architecture behavioral of cd4ce_mxilinx_hour
# -- Compiling entity hour
# -- Compiling architecture behavioral of hour
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package vcomponents
# -- Compiling entity and16_mxilinx_alarm
# -- Compiling architecture behavioral of and16_mxilinx_alarm
# -- Compiling entity alarm
# -- Compiling architecture behavioral of alarm
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package vcomponents
# -- Compiling entity clock
# -- Compiling architecture behavioral of clock
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vcomponents
# -- Loading package numeric_std
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity testclock1
# -- Compiling architecture testbench_arch of testclock1
# vsim -lib work -t 1ps testclock1 
# Loading D:\Modeltech_6.0\win32/../std.standard
# Loading D:\Modeltech_6.0\win32/../ieee.std_logic_1164(body)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.vcomponents
# Loading D:\Modeltech_6.0\win32/../ieee.numeric_std(body)
# Loading D:\Modeltech_6.0\win32/../std.textio(body)
# Loading D:\Modeltech_6.0\win32/../ieee.std_logic_textio(body)
# Loading work.testclock1(testbench_arch)
# Loading work.clock(behavioral)
# Loading work.plus60(behavioral)
# Loading work.cd4ce_mxilinx_plus60(behavioral)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.fdce(fdce_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.and3(and3_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.xor2(xor2_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.or2(or2_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.and2(and2_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.and2b1(and2b1_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.inv(inv_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.and4b2(and4b2_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.and5b2(and5b2_v)
# Loading work.hour(behavioral)
# Loading work.cd4ce_mxilinx_hour(behavioral)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.and4b3(and4b3_v)
# Loading work.alarm(behavioral)
# Loading work.and16_mxilinx_alarm(behavioral)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.muxcy_l(muxcy_l_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.fmap(fmap_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.vcc(vcc_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.gnd(gnd_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.and4(and4_v)
# Loading d:\Modeltech_6.0\Xilinx_lib\unisim.muxcy(muxcy_v)
# .wave
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Failure: Simulation successful (not a failure).  No problems detected.
#    Time: 10000205 ns  Iteration: 0  Process: /testclock1/line__164 File: testclock1.vhw
# Break at testclock1.vhw line 738
# Simulation Breakpoint: Break at testclock1.vhw line 738
# MACRO ./testclock1.fdo PAUSED at line 16