clock.syr

XLINX做的数字钟

#      AND3                        : 10
#      AND4                        : 4
#      AND4b2                      : 15
#      AND4b3                      : 2
#      AND5b2                      : 3
#      GND                         : 1
#      INV                         : 17
#      MUXCY                       : 1
#      MUXCY_L                     : 3
#      OR2                         : 17
#      VCC                         : 3
#      XOR2                        : 46
# FlipFlops/Latches                : 45
#      FD                          : 5
#      FDCE                        : 40
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 33
#      IBUF                        : 7
#      OBUF                        : 26
# Others                           : 4
#      FMAP                        : 4
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v100pq240-4 

 Number of Slices:                      25  out of   1200     2%  
 Number of Slice Flip Flops:            45  out of   2400     1%  
 Number of bonded IOBs:                 34  out of    170    20%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+----------------------------+-------+
Clock Signal                       | Clock buffer(FF name)      | Load  |
-----------------------------------+----------------------------+-------+
CLOCK                              | BUFGP                      | 28    |
XLXN_83(XLXI_5:O)                  | NONE(*)(XLXI_3/XLXI_1/I_Q0)| 8     |
XLXN_56(XLXI_22:O)                 | NONE(*)(XLXI_2/XLXI_2/I_Q3)| 9     |
-----------------------------------+----------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.566ns (Maximum Frequency: 94.643MHz)
   Minimum input arrival time before clock: 5.854ns
   Maximum output required time after clock: 14.406ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLOCK'
  Clock period: 10.478ns (frequency: 95.438MHz)
  Total number of paths / destination ports: 115 / 39
-------------------------------------------------------------------------
Delay:               10.478ns (Levels of Logic = 3)
  Source:            XLXI_9/XLXI_2/XLXI_2/I_Q0 (FF)
  Destination:       XLXI_9/XLXI_2/XLXI_2/I_Q3 (FF)
  Source Clock:      CLOCK rising
  Destination Clock: CLOCK rising

  Data Path: XLXI_9/XLXI_2/XLXI_2/I_Q0 to XLXI_9/XLXI_2/XLXI_2/I_Q3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             9   1.372   2.332  I_Q0 (Q0)
     AND3:I1->O            1   0.738   1.265  I_36_70 (A03B)
     OR2:I1->O             1   0.738   1.265  I_36_75 (OX3)
     XOR2:I1->O            1   0.738   1.265  I_36_73 (D3)
     FDCE:D                    0.765          I_Q3
    ----------------------------------------
    Total                     10.478ns (4.351ns logic, 6.127ns route)
                                       (41.5% logic, 58.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_5:O'
  Clock period: 10.566ns (frequency: 94.643MHz)
  Total number of paths / destination ports: 42 / 12
-------------------------------------------------------------------------
Delay:               10.566ns (Levels of Logic = 3)
  Source:            XLXI_3/XLXI_2/I_Q0 (FF)
  Destination:       XLXI_3/XLXI_2/I_Q3 (FF)
  Source Clock:      XLXI_5:O rising
  Destination Clock: XLXI_5:O rising

  Data Path: XLXI_3/XLXI_2/I_Q0 to XLXI_3/XLXI_2/I_Q3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            10   1.372   2.420  I_Q0 (Q0)
     AND3:I1->O            1   0.738   1.265  I_36_70 (A03B)
     OR2:I1->O             1   0.738   1.265  I_36_75 (OX3)
     XOR2:I1->O            1   0.738   1.265  I_36_73 (D3)
     FDCE:D                    0.765          I_Q3
    ----------------------------------------
    Total                     10.566ns (4.351ns logic, 6.215ns route)
                                       (41.2% logic, 58.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_22:O'
  Clock period: 10.566ns (frequency: 94.643MHz)
  Total number of paths / destination ports: 34 / 13
-------------------------------------------------------------------------
Delay:               10.566ns (Levels of Logic = 3)
  Source:            XLXI_2/XLXI_1/I_Q0 (FF)
  Destination:       XLXI_2/XLXI_1/I_Q3 (FF)
  Source Clock:      XLXI_22:O rising
  Destination Clock: XLXI_22:O rising

  Data Path: XLXI_2/XLXI_1/I_Q0 to XLXI_2/XLXI_1/I_Q3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            10   1.372   2.420  I_Q0 (Q0)
     AND3:I1->O            1   0.738   1.265  I_36_70 (A03B)
     OR2:I1->O             1   0.738   1.265  I_36_75 (OX3)
     XOR2:I1->O            1   0.738   1.265  I_36_73 (D3)
     FDCE:D                    0.765          I_Q3
    ----------------------------------------
    Total                     10.566ns (4.351ns logic, 6.215ns route)
                                       (41.2% logic, 58.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
  Total number of paths / destination ports: 12 / 12
-------------------------------------------------------------------------
Offset:              5.854ns (Levels of Logic = 3)
  Source:            ALMSETH (PAD)
  Destination:       XLXI_9/XLXI_2/XLXI_2/I_Q0 (FF)
  Destination Clock: CLOCK rising

  Data Path: ALMSETH to XLXI_9/XLXI_2/XLXI_2/I_Q0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.989   1.265  ALMSETH_IBUF (ALMSETH_IBUF)
     INV:I->O              5   0.738   1.914  XLXI_12 (XLXN_11)
     begin scope: 'XLXI_9/XLXI_2/XLXI_2'
     FDCE:CE                   0.948          I_Q0
    ----------------------------------------
    Total                      5.854ns (2.675ns logic, 3.179ns route)
                                       (45.7% logic, 54.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_22:O'
  Total number of paths / destination ports: 16 / 9
-------------------------------------------------------------------------
Offset:              14.406ns (Levels of Logic = 8)
  Source:            XLXI_2/XLXI_1/I_Q0 (FF)
  Destination:       ALARMOUT (PAD)
  Source Clock:      XLXI_22:O rising

  Data Path: XLXI_2/XLXI_1/I_Q0 to ALARMOUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            10   1.372   2.420  I_Q0 (Q0)
     end scope: 'XLXI_2/XLXI_1'
     XOR2:I0->O            1   0.738   1.265  XLXI_9/XLXI_19 (XLXI_9/MHO0)
     begin scope: 'XLXI_9/XLXI_30'
     AND4:I3->O            1   0.738   0.000  I_36_127 (S1)
     MUXCY_L:S->LO         1   0.842   0.000  I_36_129 (C1)
     MUXCY_L:CI->LO        1   0.057   0.000  I_36_147 (C2)
     MUXCY:CI->O           1   0.057   1.265  I_36_165 (O)
     end scope: 'XLXI_9/XLXI_30'
     OBUF:I->O                 5.652          ALARMOUT_OBUF (ALARMOUT)
    ----------------------------------------
    Total                     14.406ns (9.456ns logic, 4.950ns route)
                                       (65.6% logic, 34.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
  Total number of paths / destination ports: 26 / 10
-------------------------------------------------------------------------
Offset:              14.318ns (Levels of Logic = 8)
  Source:            XLXI_9/XLXI_1/XLXI_1/I_Q0 (FF)
  Destination:       ALARMOUT (PAD)
  Source Clock:      CLOCK rising

  Data Path: XLXI_9/XLXI_1/XLXI_1/I_Q0 to ALARMOUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             9   1.372   2.332  I_Q0 (Q0)
     end scope: 'XLXI_9/XLXI_1/XLXI_1'
     XOR2:I1->O            1   0.738   1.265  XLXI_9/XLXI_19 (XLXI_9/MHO0)
     begin scope: 'XLXI_9/XLXI_30'
     AND4:I3->O            1   0.738   0.000  I_36_127 (S1)
     MUXCY_L:S->LO         1   0.842   0.000  I_36_129 (C1)
     MUXCY_L:CI->LO        1   0.057   0.000  I_36_147 (C2)
     MUXCY:CI->O           1   0.057   1.265  I_36_165 (O)
     end scope: 'XLXI_9/XLXI_30'
     OBUF:I->O                 5.652          ALARMOUT_OBUF (ALARMOUT)
    ----------------------------------------
    Total                     14.318ns (9.456ns logic, 4.862ns route)
                                       (66.0% logic, 34.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_5:O'
  Total number of paths / destination ports: 16 / 9
-------------------------------------------------------------------------
Offset:              14.349ns (Levels of Logic = 7)
  Source:            XLXI_3/XLXI_2/I_Q0 (FF)
  Destination:       ALARMOUT (PAD)
  Source Clock:      XLXI_5:O rising

  Data Path: XLXI_3/XLXI_2/I_Q0 to ALARMOUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            10   1.372   2.420  I_Q0 (Q0)
     end scope: 'XLXI_3/XLXI_2'
     XOR2:I0->O            1   0.738   1.265  XLXI_9/XLXI_9 (XLXI_9/HLO0)
     begin scope: 'XLXI_9/XLXI_30'
     AND4:I3->O            1   0.738   0.000  I_36_151 (S2)
     MUXCY_L:S->LO         1   0.842   0.000  I_36_147 (C2)
     MUXCY:CI->O           1   0.057   1.265  I_36_165 (O)
     end scope: 'XLXI_9/XLXI_30'
     OBUF:I->O                 5.652          ALARMOUT_OBUF (ALARMOUT)
    ----------------------------------------
    Total                     14.349ns (9.399ns logic, 4.950ns route)
                                       (65.5% logic, 34.5% route)

=========================================================================
CPU : 3.66 / 3.89 s | Elapsed : 4.00 / 4.00 s
 
--> 

Total memory usage is 88624 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    8 (   0 filtered)
Number of infos    :    1 (   0 filtered)