📄 alarm.vhf
字号:
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1i
-- \ \ Application : sch2vhdl
-- / / Filename : alarm.vhf
-- /___/ /\ Timestamp : 06/21/2008 20:00:55
-- \ \ / \
-- \___\/\___\
--
--Command: D:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family virtex -flat -suppress -w alarm.sch alarm.vhf
--Design Name: alarm
--Device: virtex
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity AND16_MXILINX_alarm is
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic;
I6 : in std_logic;
I7 : in std_logic;
I8 : in std_logic;
I9 : in std_logic;
I10 : in std_logic;
I11 : in std_logic;
I12 : in std_logic;
I13 : in std_logic;
I14 : in std_logic;
I15 : in std_logic;
O : out std_logic);
end AND16_MXILINX_alarm;
architecture BEHAVIORAL of AND16_MXILINX_alarm is
attribute BOX_TYPE : string ;
attribute RLOC : string ;
signal CIN : std_logic;
signal C0 : std_logic;
signal C1 : std_logic;
signal C2 : std_logic;
signal S0 : std_logic;
signal S1 : std_logic;
signal S2 : std_logic;
signal S3 : std_logic;
signal XLXN_1 : std_logic;
component MUXCY_L
port ( CI : in std_logic;
DI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
attribute BOX_TYPE of MUXCY_L : component is "BLACK_BOX";
component FMAP
port ( I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
O : in std_logic);
end component;
attribute BOX_TYPE of FMAP : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component AND4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
component MUXCY
port ( CI : in std_logic;
DI : in std_logic;
S : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of MUXCY : component is "BLACK_BOX";
attribute RLOC of I_36_2 : label is "R1C0.S1";
attribute RLOC of I_36_29 : label is "R1C0.S1";
attribute RLOC of I_36_129 : label is "R1C0.S1";
attribute RLOC of I_36_138 : label is "R1C0.S1";
attribute RLOC of I_36_142 : label is "R0C0.S1";
attribute RLOC of I_36_147 : label is "R0C0.S1";
attribute RLOC of I_36_165 : label is "R0C0.S1";
attribute RLOC of I_36_170 : label is "R0C0.S1";
begin
I_36_2 : MUXCY_L
port map (CI=>CIN,
DI=>XLXN_1,
S=>S0,
LO=>C0);
I_36_29 : FMAP
port map (I1=>I0,
I2=>I1,
I3=>I2,
I4=>I3,
O=>S0);
I_36_107 : VCC
port map (P=>CIN);
I_36_109 : GND
port map (G=>XLXN_1);
I_36_110 : AND4
port map (I0=>I0,
I1=>I1,
I2=>I2,
I3=>I3,
O=>S0);
I_36_127 : AND4
port map (I0=>I4,
I1=>I5,
I2=>I6,
I3=>I7,
O=>S1);
I_36_129 : MUXCY_L
port map (CI=>C0,
DI=>XLXN_1,
S=>S1,
LO=>C1);
I_36_138 : FMAP
port map (I1=>I4,
I2=>I5,
I3=>I6,
I4=>I7,
O=>S1);
I_36_142 : FMAP
port map (I1=>I8,
I2=>I9,
I3=>I10,
I4=>I11,
O=>S2);
I_36_147 : MUXCY_L
port map (CI=>C1,
DI=>XLXN_1,
S=>S2,
LO=>C2);
I_36_151 : AND4
port map (I0=>I8,
I1=>I9,
I2=>I10,
I3=>I11,
O=>S2);
I_36_161 : AND4
port map (I0=>I12,
I1=>I13,
I2=>I14,
I3=>I15,
O=>S3);
I_36_165 : MUXCY
port map (CI=>C2,
DI=>XLXN_1,
S=>S3,
O=>O);
I_36_170 : FMAP
port map (I1=>I12,
I2=>I13,
I3=>I14,
I4=>I15,
O=>S3);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity alarm is
port ( CLOCK : in std_logic;
CLR : in std_logic;
HHI0 : in std_logic;
HHI1 : in std_logic;
HHI2 : in std_logic;
HHI3 : in std_logic;
HLI0 : in std_logic;
HLI1 : in std_logic;
HLI2 : in std_logic;
HLI3 : in std_logic;
HSET : in std_logic;
MHI0 : in std_logic;
MHI1 : in std_logic;
MHI2 : in std_logic;
MHI3 : in std_logic;
MLI0 : in std_logic;
MLI1 : in std_logic;
MLI2 : in std_logic;
MLI3 : in std_logic;
MSET : in std_logic;
ALARMOUT : out std_logic);
end alarm;
architecture BEHAVIORAL of alarm is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal HHO0 : std_logic;
signal HHO1 : std_logic;
signal HHO2 : std_logic;
signal HHO3 : std_logic;
signal HH0 : std_logic;
signal HH1 : std_logic;
signal HH2 : std_logic;
signal HH3 : std_logic;
signal HLO0 : std_logic;
signal HLO1 : std_logic;
signal HLO2 : std_logic;
signal HLO3 : std_logic;
signal HL0 : std_logic;
signal HL1 : std_logic;
signal HL2 : std_logic;
signal HL3 : std_logic;
signal MHO0 : std_logic;
signal MHO1 : std_logic;
signal MHO2 : std_logic;
signal MHO3 : std_logic;
signal MH0 : std_logic;
signal MH1 : std_logic;
signal MH2 : std_logic;
signal MH3 : std_logic;
signal MLO0 : std_logic;
signal MLO1 : std_logic;
signal MLO2 : std_logic;
signal MLO3 : std_logic;
signal ML0 : std_logic;
signal ML1 : std_logic;
signal ML2 : std_logic;
signal ML3 : std_logic;
component Plus60
port ( SET1 : in std_logic;
CLOCK : in std_logic;
CLR : in std_logic;
PLUS59 : out std_logic;
L0 : out std_logic;
H0 : out std_logic;
L1 : out std_logic;
H1 : out std_logic;
L2 : out std_logic;
H2 : out std_logic;
L3 : out std_logic;
H3 : out std_logic);
end component;
component Hour
port ( INPUT_M : in std_logic;
CLOCK : in std_logic;
CLR : in std_logic;
L0 : out std_logic;
H0 : out std_logic;
L1 : out std_logic;
H1 : out std_logic;
L2 : out std_logic;
H2 : out std_logic;
L3 : out std_logic;
H3 : out std_logic);
end component;
component XOR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of XOR2 : component is "BLACK_BOX";
component AND16_MXILINX_alarm
port ( I0 : in std_logic;
I1 : in std_logic;
I10 : in std_logic;
I11 : in std_logic;
I12 : in std_logic;
I13 : in std_logic;
I14 : in std_logic;
I15 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic;
I6 : in std_logic;
I7 : in std_logic;
I8 : in std_logic;
I9 : in std_logic;
O : out std_logic);
end component;
attribute HU_SET of XLXI_30 : label is "XLXI_30_0";
begin
XLXI_1 : Plus60
port map (CLOCK=>CLOCK,
CLR=>CLR,
SET1=>MSET,
H0=>MH0,
H1=>MH1,
H2=>MH2,
H3=>MH3,
L0=>ML0,
L1=>ML1,
L2=>ML2,
L3=>ML3,
PLUS59=>open);
XLXI_2 : Hour
port map (CLOCK=>CLOCK,
CLR=>CLR,
INPUT_M=>HSET,
H0=>HH0,
H1=>HH1,
H2=>HH2,
H3=>HH3,
L0=>HL0,
L1=>HL1,
L2=>HL2,
L3=>HL3);
XLXI_5 : XOR2
port map (I0=>HHI0,
I1=>HH0,
O=>HHO0);
XLXI_6 : XOR2
port map (I0=>HHI1,
I1=>HH1,
O=>HHO1);
XLXI_7 : XOR2
port map (I0=>HHI2,
I1=>HH2,
O=>HHO2);
XLXI_8 : XOR2
port map (I0=>HHI3,
I1=>HH3,
O=>HHO3);
XLXI_9 : XOR2
port map (I0=>HLI0,
I1=>HL0,
O=>HLO0);
XLXI_10 : XOR2
port map (I0=>HLI1,
I1=>HL1,
O=>HLO1);
XLXI_11 : XOR2
port map (I0=>HLI2,
I1=>HL2,
O=>HLO2);
XLXI_12 : XOR2
port map (I0=>HLI3,
I1=>HL3,
O=>HLO3);
XLXI_13 : XOR2
port map (I0=>MHI1,
I1=>MH1,
O=>MHO1);
XLXI_14 : XOR2
port map (I0=>MLI0,
I1=>ML0,
O=>MLO0);
XLXI_15 : XOR2
port map (I0=>MHI2,
I1=>MH2,
O=>MHO2);
XLXI_16 : XOR2
port map (I0=>MLI1,
I1=>ML1,
O=>MLO1);
XLXI_17 : XOR2
port map (I0=>MHI3,
I1=>MH3,
O=>MHO3);
XLXI_18 : XOR2
port map (I0=>MLI2,
I1=>ML2,
O=>MLO2);
XLXI_19 : XOR2
port map (I0=>MHI0,
I1=>MH0,
O=>MHO0);
XLXI_20 : XOR2
port map (I0=>MLI3,
I1=>ML3,
O=>MLO3);
XLXI_30 : AND16_MXILINX_alarm
port map (I0=>MLO3,
I1=>MLO2,
I2=>MLO1,
I3=>MLO0,
I4=>MHO3,
I5=>MHO2,
I6=>MHO1,
I7=>MHO0,
I8=>HLO3,
I9=>HLO2,
I10=>HLO1,
I11=>HLO0,
I12=>HHO3,
I13=>HHO2,
I14=>HHO1,
I15=>HHO0,
O=>ALARMOUT);
end BEHAVIORAL;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -