test60.tbw

XLINX做的数字钟

version 3
h:\学习\数字逻辑课程设计\book\数字钟\Plus60.vhf
Plus60
VHDL
VHDL
test60.xwv
Clocked
-
-
10000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
CLOCK
100000000
100000000
15000000
15000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
CLR
CLOCK
H0
CLOCK
H1
CLOCK
H2
CLOCK
H3
CLOCK
L0
CLOCK
L1
CLOCK
L2
CLOCK
L3
CLOCK
SET1
CLOCK
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
H0_DIFF
H1_DIFF
H2_DIFF
H3_DIFF
L0_DIFF
L1_DIFF
L2_DIFF
L3_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
CLOCK
CLR
SET1
H0
H1
H2
H3
L0
L1
L2
L3
SIGNAL_ORDER_END
-X-X-X-