alarm_synthesis.vhd

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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.38
--  \   \         Application: netgen
--  /   /         Filename: alarm_synthesis.vhd
-- /___/   /\     Timestamp: Sat Jun 21 19:18:46 2008
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command: -intstyle ise -ar Structure -w -ofmt vhdl -sim alarm.ngc alarm_synthesis.vhd 
-- Device: xcv100-4-pq240
-- Design Name: alarm
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity alarm is
  port (
    CLR : in STD_LOGIC := 'X'; 
    HHI0 : in STD_LOGIC := 'X'; 
    HHI1 : in STD_LOGIC := 'X'; 
    HHI2 : in STD_LOGIC := 'X'; 
    HHI3 : in STD_LOGIC := 'X'; 
    SET1 : in STD_LOGIC := 'X'; 
    MHI0 : in STD_LOGIC := 'X'; 
    MHI1 : in STD_LOGIC := 'X'; 
    MHI2 : in STD_LOGIC := 'X'; 
    MHI3 : in STD_LOGIC := 'X'; 
    HLI0 : in STD_LOGIC := 'X'; 
    HLI1 : in STD_LOGIC := 'X'; 
    HLI2 : in STD_LOGIC := 'X'; 
    HLI3 : in STD_LOGIC := 'X'; 
    MLI0 : in STD_LOGIC := 'X'; 
    MLI1 : in STD_LOGIC := 'X'; 
    MLI2 : in STD_LOGIC := 'X'; 
    MLI3 : in STD_LOGIC := 'X'; 
    INPUTH : in STD_LOGIC := 'X'; 
    INPUTM : in STD_LOGIC := 'X'; 
    ALARMOUT : out STD_LOGIC; 
    OUTPUT59 : out STD_LOGIC 
  );
end alarm;

architecture Structure of alarm is
  signal CLR_IBUF : STD_LOGIC; 
  signal HHI0_IBUF : STD_LOGIC; 
  signal HHI1_IBUF : STD_LOGIC; 
  signal HHI2_IBUF : STD_LOGIC; 
  signal HHI3_IBUF : STD_LOGIC; 
  signal ALARMOUT_OBUF : STD_LOGIC; 
  signal SET1_IBUF : STD_LOGIC; 
  signal MHI0_IBUF : STD_LOGIC; 
  signal MHI1_IBUF : STD_LOGIC; 
  signal MHI2_IBUF : STD_LOGIC; 
  signal MHI3_IBUF : STD_LOGIC; 
  signal HLI0_IBUF : STD_LOGIC; 
  signal HLI1_IBUF : STD_LOGIC; 
  signal HLI2_IBUF : STD_LOGIC; 
  signal HLI3_IBUF : STD_LOGIC; 
  signal MLI0_IBUF : STD_LOGIC; 
  signal MLI1_IBUF : STD_LOGIC; 
  signal MLI2_IBUF : STD_LOGIC; 
  signal MLI3_IBUF : STD_LOGIC; 
  signal OUTPUT59_OBUF : STD_LOGIC; 
  signal INPUTH_BUFGP : STD_LOGIC; 
  signal INPUTM_BUFGP : STD_LOGIC; 
  signal MLO0 : STD_LOGIC; 
  signal MLO1 : STD_LOGIC; 
  signal MLO2 : STD_LOGIC; 
  signal MLO3 : STD_LOGIC; 
  signal MH0 : STD_LOGIC; 
  signal MH1 : STD_LOGIC; 
  signal MH2 : STD_LOGIC; 
  signal MH3 : STD_LOGIC; 
  signal ML0 : STD_LOGIC; 
  signal ML1 : STD_LOGIC; 
  signal ML2 : STD_LOGIC; 
  signal ML3 : STD_LOGIC; 
  signal HHO0 : STD_LOGIC; 
  signal HHO1 : STD_LOGIC; 
  signal HHO2 : STD_LOGIC; 
  signal HHO3 : STD_LOGIC; 
  signal HH0 : STD_LOGIC; 
  signal HH1 : STD_LOGIC; 
  signal HH2 : STD_LOGIC; 
  signal HH3 : STD_LOGIC; 
  signal MHO0 : STD_LOGIC; 
  signal MHO1 : STD_LOGIC; 
  signal MHO2 : STD_LOGIC; 
  signal MHO3 : STD_LOGIC; 
  signal HL0 : STD_LOGIC; 
  signal HL1 : STD_LOGIC; 
  signal HL2 : STD_LOGIC; 
  signal HL3 : STD_LOGIC; 
  signal HLO0 : STD_LOGIC; 
  signal HLO1 : STD_LOGIC; 
  signal HLO2 : STD_LOGIC; 
  signal HLO3 : STD_LOGIC; 
  signal XLXI_1_XLXN_2 : STD_LOGIC; 
  signal XLXI_1_XLXN_13 : STD_LOGIC; 
  signal XLXI_1_XLXN_3 : STD_LOGIC; 
  signal XLXI_2_XLXN_31 : STD_LOGIC; 
  signal XLXI_2_XLXN_38 : STD_LOGIC; 
  signal XLXI_2_XLXN_37 : STD_LOGIC; 
  signal XLXI_2_XLXN_39 : STD_LOGIC; 
  signal XLXI_2_CLR1 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_OX3 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_AO3A : STD_LOGIC; 
  signal XLXI_1_XLXI_1_A03B : STD_LOGIC; 
  signal XLXI_1_XLXI_1_AX2 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_D3 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_D2 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_D1 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_D0 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_AX1 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_CEO : STD_LOGIC; 
  signal XLXI_1_XLXI_1_TC : STD_LOGIC; 
  signal XLXI_2_XLXI_1_OX3 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_AO3A : STD_LOGIC; 
  signal XLXI_2_XLXI_1_A03B : STD_LOGIC; 
  signal XLXI_2_XLXI_1_AX2 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_D3 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_D2 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_D1 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_D0 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_AX1 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_CEO : STD_LOGIC; 
  signal XLXI_2_XLXI_1_TC : STD_LOGIC; 
  signal XLXI_30_C2 : STD_LOGIC; 
  signal XLXI_30_C1 : STD_LOGIC; 
  signal XLXI_30_C0 : STD_LOGIC; 
  signal XLXI_30_CIN : STD_LOGIC; 
  signal XLXI_30_XLXN_1 : STD_LOGIC; 
  signal XLXI_30_S3 : STD_LOGIC; 
  signal XLXI_30_S2 : STD_LOGIC; 
  signal XLXI_30_S1 : STD_LOGIC; 
  signal XLXI_30_S0 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_OX3 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_AO3A : STD_LOGIC; 
  signal XLXI_1_XLXI_2_A03B : STD_LOGIC; 
  signal XLXI_1_XLXI_2_AX2 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_D3 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_D2 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_D1 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_D0 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_AX1 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_CEO : STD_LOGIC; 
  signal XLXI_1_XLXI_2_TC : STD_LOGIC; 
  signal XLXI_2_XLXI_2_OX3 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_AO3A : STD_LOGIC; 
  signal XLXI_2_XLXI_2_A03B : STD_LOGIC; 
  signal XLXI_2_XLXI_2_AX2 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_D3 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_D2 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_D1 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_D0 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_AX1 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_CEO : STD_LOGIC; 
  signal XLXI_2_XLXI_2_TC : STD_LOGIC; 
begin
  XLXI_5 : XOR2
    port map (
      I0 => HHI0_IBUF,
      I1 => HH0,
      O => HHO0
    );
  XLXI_6 : XOR2
    port map (
      I0 => HHI1_IBUF,
      I1 => HH1,
      O => HHO1
    );
  XLXI_7 : XOR2
    port map (
      I0 => HHI2_IBUF,
      I1 => HH2,
      O => HHO2
    );
  XLXI_8 : XOR2
    port map (
      I0 => HHI3_IBUF,
      I1 => HH3,
      O => HHO3
    );
  XLXI_9 : XOR2
    port map (
      I0 => HLI0_IBUF,
      I1 => HL0,
      O => HLO0
    );
  XLXI_10 : XOR2
    port map (
      I0 => HLI1_IBUF,
      I1 => HL1,
      O => HLO1
    );
  XLXI_11 : XOR2
    port map (
      I0 => HLI2_IBUF,
      I1 => HL2,
      O => HLO2
    );
  XLXI_12 : XOR2
    port map (
      I0 => HLI3_IBUF,
      I1 => HL3,
      O => HLO3
    );
  XLXI_13 : XOR2
    port map (
      I0 => MHI1_IBUF,
      I1 => MH1,
      O => MHO1
    );
  XLXI_14 : XOR2
    port map (
      I0 => MLI0_IBUF,
      I1 => ML0,
      O => MLO0
    );
  XLXI_15 : XOR2
    port map (
      I0 => MHI2_IBUF,
      I1 => MH2,
      O => MHO2
    );
  XLXI_16 : XOR2
    port map (
      I0 => MLI1_IBUF,
      I1 => ML1,
      O => MLO1
    );
  XLXI_17 : XOR2
    port map (
      I0 => MHI3_IBUF,
      I1 => MH3,
      O => MHO3
    );
  XLXI_18 : XOR2
    port map (
      I0 => MLI2_IBUF,
      I1 => ML2,
      O => MLO2
    );
  XLXI_19 : XOR2
    port map (
      I0 => MHI0_IBUF,
      I1 => MH0,
      O => MHO0
    );
  XLXI_20 : XOR2
    port map (
      I0 => MLI3_IBUF,
      I1 => ML3,
      O => MLO3
    );
  XLXI_1_XLXI_7 : AND5b2
    port map (
      I0 => MH3,
      I1 => MH1,
      I2 => MH2,
      I3 => MH0,
      I4 => XLXI_1_XLXN_13,
      O => OUTPUT59_OBUF
    );
  XLXI_1_XLXI_5 : OR2
    port map (
      I0 => XLXI_1_XLXN_3,
      I1 => CLR_IBUF,
      O => XLXI_1_XLXN_2
    );
  XLXI_1_XLXI_4 : AND4b2
    port map (
      I0 => MH3,
      I1 => MH0,
      I2 => MH2,
      I3 => MH1,
      O => XLXI_1_XLXN_3
    );
  XLXI_1_XLXI_3 : AND4b2
    port map (
      I0 => ML2,
      I1 => ML1,
      I2 => ML3,
      I3 => ML0,
      O => XLXI_1_XLXN_13
    );
  XLXI_2_XLXI_13 : AND2
    port map (
      I0 => XLXI_2_XLXN_39,
      I1 => XLXI_2_XLXN_38,
      O => XLXI_2_XLXN_37
    );
  XLXI_2_XLXI_12 : AND4b3
    port map (
      I0 => HL3,
      I1 => HL1,
      I2 => HL0,
      I3 => HL2,
      O => XLXI_2_XLXN_39
    );
  XLXI_2_XLXI_11 : AND4b3
    port map (
      I0 => HH3,
      I1 => HH2,
      I2 => HH0,
      I3 => HH1,
      O => XLXI_2_XLXN_38
    );
  XLXI_2_XLXI_10 : OR2
    port map (
      I0 => XLXI_2_XLXN_37,
      I1 => CLR_IBUF,
      O => XLXI_2_CLR1
    );
  XLXI_2_XLXI_3 : AND4b2
    port map (
      I0 => HL2,
      I1 => HL1,
      I2 => HL0,
      I3 => HL3,
      O => XLXI_2_XLXN_31
    );
  INPUTH_BUFGP_0 : BUFGP
    port map (
      I => INPUTH,
      O => INPUTH_BUFGP
    );
  INPUTM_BUFGP_1 : BUFGP
    port map (
      I => INPUTM,
      O => INPUTM_BUFGP
    );
  CLR_IBUF_2 : IBUF
    port map (
      I => CLR,
      O => CLR_IBUF
    );
  HHI0_IBUF_3 : IBUF
    port map (
      I => HHI0,
      O => HHI0_IBUF
    );
  HHI1_IBUF_4 : IBUF
    port map (
      I => HHI1,
      O => HHI1_IBUF
    );
  HHI2_IBUF_5 : IBUF
    port map (
      I => HHI2,
      O => HHI2_IBUF
    );
  HHI3_IBUF_6 : IBUF
    port map (
      I => HHI3,
      O => HHI3_IBUF
    );
  SET1_IBUF_7 : IBUF
    port map (
      I => SET1,
      O => SET1_IBUF
    );
  MHI0_IBUF_8 : IBUF
    port map (
      I => MHI0,
      O => MHI0_IBUF
    );
  MHI1_IBUF_9 : IBUF
    port map (
      I => MHI1,
      O => MHI1_IBUF
    );
  MHI2_IBUF_10 : IBUF
    port map (
      I => MHI2,
      O => MHI2_IBUF
    );
  MHI3_IBUF_11 : IBUF
    port map (
      I => MHI3,
      O => MHI3_IBUF
    );
  HLI0_IBUF_12 : IBUF
    port map (
      I => HLI0,
      O => HLI0_IBUF
    );
  HLI1_IBUF_13 : IBUF
    port map (
      I => HLI1,
      O => HLI1_IBUF
    );
  HLI2_IBUF_14 : IBUF
    port map (
      I => HLI2,
      O => HLI2_IBUF
    );
  HLI3_IBUF_15 : IBUF
    port map (
      I => HLI3,
      O => HLI3_IBUF
    );
  MLI0_IBUF_16 : IBUF
    port map (
      I => MLI0,
      O => MLI0_IBUF
    );
  MLI1_IBUF_17 : IBUF
    port map (
      I => MLI1,
      O => MLI1_IBUF
    );
  MLI2_IBUF_18 : IBUF
    port map (
      I => MLI2,
      O => MLI2_IBUF
    );
  MLI3_IBUF_19 : IBUF
    port map (
      I => MLI3,
      O => MLI3_IBUF
    );
  ALARMOUT_OBUF_20 : OBUF
    port map (
      I => ALARMOUT_OBUF,
      O => ALARMOUT
    );
  OUTPUT59_OBUF_21 : OBUF
    port map (
      I => OUTPUT59_OBUF,
      O => OUTPUT59
    );
  XLXI_1_XLXI_1_I_36_81 : AND2b1
    port map (
      I0 => MH3,
      I1 => MH0,
      O => XLXI_1_XLXI_1_AX1
    );
  XLXI_1_XLXI_1_I_36_78 : XOR2
    port map (
      I0 => MH2,
      I1 => XLXI_1_XLXI_1_AX2,
      O => XLXI_1_XLXI_1_D2
    );
  XLXI_1_XLXI_1_I_36_77 : AND2
    port map (
      I0 => MH0,
      I1 => MH1,
      O => XLXI_1_XLXI_1_AX2
    );
  XLXI_1_XLXI_1_I_36_75 : OR2
    port map (
      I0 => XLXI_1_XLXI_1_AO3A,
      I1 => XLXI_1_XLXI_1_A03B,
      O => XLXI_1_XLXI_1_OX3
    );
  XLXI_1_XLXI_1_I_36_73 : XOR2
    port map (
      I0 => MH3,
      I1 => XLXI_1_XLXI_1_OX3,
      O => XLXI_1_XLXI_1_D3
    );
  XLXI_1_XLXI_1_I_36_70 : AND3
    port map (
      I0 => MH2,
      I1 => MH0,
      I2 => MH1,
      O => XLXI_1_XLXI_1_A03B
    );
  XLXI_1_XLXI_1_I_Q3 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => XLXI_1_XLXI_1_D3,
      CE => XLXI_1_XLXN_13,
      CLR => XLXI_1_XLXN_2,
      C => INPUTM_BUFGP,
      Q => MH3
    );
  XLXI_1_XLXI_1_I_Q2 : FDCE
    generic map(