📄 test60.ant
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1i
-- \ \ Application : ISE Foundation
-- / / Filename : test60.ant
-- /___/ /\ Timestamp : Tue Jun 17 21:50:13 2008
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: test60
--Device: Xilinx
--
library UNISIM;
use UNISIM.Vcomponents.ALL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY test60 IS
END test60;
ARCHITECTURE testbench_arch OF test60 IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "H:\学习\数字逻辑课程设计\book\数字钟\test60.ano";
COMPONENT Plus60
PORT (
CLOCK : In std_logic;
CLR : In std_logic;
SET1 : In std_logic;
H0 : Out std_logic;
H1 : Out std_logic;
H2 : Out std_logic;
H3 : Out std_logic;
L0 : Out std_logic;
L1 : Out std_logic;
L2 : Out std_logic;
L3 : Out std_logic
);
END COMPONENT;
SIGNAL CLOCK : std_logic := '0';
SIGNAL CLR : std_logic := '0';
SIGNAL SET1 : std_logic := '0';
SIGNAL H0 : std_logic := '0';
SIGNAL H1 : std_logic := '0';
SIGNAL H2 : std_logic := '0';
SIGNAL H3 : std_logic := '0';
SIGNAL L0 : std_logic := '0';
SIGNAL L1 : std_logic := '0';
SIGNAL L2 : std_logic := '0';
SIGNAL L3 : std_logic := '0';
SHARED VARIABLE TX_ERROR : INTEGER := 0;
SHARED VARIABLE TX_OUT : LINE;
constant PERIOD : time := 200 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 0 ns;
BEGIN
UUT : Plus60
PORT MAP (
CLOCK => CLOCK,
CLR => CLR,
SET1 => SET1,
H0 => H0,
H1 => H1,
H2 => H2,
H3 => H3,
L0 => L0,
L1 => L1,
L2 => L2,
L3 => L3
);
PROCESS -- clock process for CLOCK
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
CLOCK <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
CLOCK <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS -- Annotation process for CLOCK
VARIABLE TX_TIME : INTEGER := 0;
PROCEDURE ANNOTATE_H0(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", H0, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, H0);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_H1(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", H1, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, H1);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_H2(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", H2, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, H2);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_H3(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", H3, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, H3);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_L0(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", L0, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, L0);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_L1(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", L1, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, L1);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_L2(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", L2, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, L2);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_L3(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", L3, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, L3);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
BEGIN
WAIT for 1 fs;
ANNOTATE_H0(0);
ANNOTATE_H1(0);
ANNOTATE_H2(0);
ANNOTATE_H3(0);
ANNOTATE_L0(0);
ANNOTATE_L1(0);
ANNOTATE_L2(0);
ANNOTATE_L3(0);
WAIT for OFFSET;
TX_TIME := TX_TIME + 0;
ANNO_LOOP : LOOP
--Rising Edge
WAIT for 115 ns;
TX_TIME := TX_TIME + 115;
ANNOTATE_H0(TX_TIME);
ANNOTATE_H1(TX_TIME);
ANNOTATE_H2(TX_TIME);
ANNOTATE_H3(TX_TIME);
ANNOTATE_L0(TX_TIME);
ANNOTATE_L1(TX_TIME);
ANNOTATE_L2(TX_TIME);
ANNOTATE_L3(TX_TIME);
WAIT for 85 ns;
TX_TIME := TX_TIME + 85;
END LOOP ANNO_LOOP;
END PROCESS;
PROCESS
BEGIN
WAIT FOR 10200 ns;
STD.TEXTIO.write(TX_OUT, string'("Total[]"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT
"Success! Simulation for annotation completed"
SEVERITY FAILURE;
END PROCESS;
END testbench_arch;
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