📄 clock.vhd
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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1i
-- \ \ Application : sch2vhdl
-- / / Filename : CLOCK.vhf
-- /___/ /\ Timestamp : 06/23/2008 21:41:08
-- \ \ / \
-- \___\/\___\
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family virtex -flat -suppress -w CLOCK.sch CLOCK.vhf
--Design Name: CLOCK
--Device: virtex
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity CLOCK is
port ( ALMCLR : in std_logic;
ALMSETH : in std_logic;
ALMSETM : in std_logic;
CLR : in std_logic;
CP : in std_logic;
HSETUP : in std_logic;
MSETUP : in std_logic;
PAUSE : in std_logic;
SET1 : in std_logic;
ALARMOUT : out std_logic;
HH0 : out std_logic;
HH1 : out std_logic;
HH2 : out std_logic;
HH3 : out std_logic;
HL0 : out std_logic;
HL1 : out std_logic;
HL2 : out std_logic;
HL3 : out std_logic;
MH0 : out std_logic;
MH1 : out std_logic;
MH2 : out std_logic;
MH3 : out std_logic;
ML0 : out std_logic;
ML1 : out std_logic;
ML2 : out std_logic;
ML3 : out std_logic;
SH0 : out std_logic;
SH1 : out std_logic;
SH2 : out std_logic;
SH3 : out std_logic;
SL0 : out std_logic;
SL1 : out std_logic;
SL2 : out std_logic;
SL3 : out std_logic);
end CLOCK;
architecture BEHAVIORAL of CLOCK is
attribute BOX_TYPE : string ;
attribute INIT : string ;
signal CLOCK : std_logic;
signal PHOUR : std_logic;
signal PM : std_logic;
signal PS : std_logic;
signal XLXN_1 : std_logic;
signal XLXN_4 : std_logic;
signal XLXN_7 : std_logic;
signal XLXN_9 : std_logic;
signal XLXN_11 : std_logic;
signal XLXN_13 : std_logic;
signal XLXN_15 : std_logic;
signal XLXN_20 : std_logic;
signal ML0_DUMMY : std_logic;
signal ML1_DUMMY : std_logic;
signal ML2_DUMMY : std_logic;
signal ML3_DUMMY : std_logic;
signal HH0_DUMMY : std_logic;
signal HH1_DUMMY : std_logic;
signal HH2_DUMMY : std_logic;
signal HH3_DUMMY : std_logic;
signal MH0_DUMMY : std_logic;
signal MH1_DUMMY : std_logic;
signal MH2_DUMMY : std_logic;
signal MH3_DUMMY : std_logic;
signal HL0_DUMMY : std_logic;
signal HL1_DUMMY : std_logic;
signal HL2_DUMMY : std_logic;
signal HL3_DUMMY : std_logic;
component Plus60
port ( SET1 : in std_logic;
CLOCK : in std_logic;
CLR : in std_logic;
PLUS59 : out std_logic;
L0 : out std_logic;
H0 : out std_logic;
L1 : out std_logic;
H1 : out std_logic;
L2 : out std_logic;
H2 : out std_logic;
L3 : out std_logic;
H3 : out std_logic);
end component;
component Hour
port ( INPUT_M : in std_logic;
CLOCK : in std_logic;
CLR : in std_logic;
L0 : out std_logic;
H0 : out std_logic;
L1 : out std_logic;
H1 : out std_logic;
L2 : out std_logic;
H2 : out std_logic;
L3 : out std_logic;
H3 : out std_logic);
end component;
component OR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component alarm
port ( HHI0 : in std_logic;
HLI0 : in std_logic;
HSET : in std_logic;
CLOCK : in std_logic;
HLI1 : in std_logic;
HHI1 : in std_logic;
CLR : in std_logic;
HHI2 : in std_logic;
HLI2 : in std_logic;
HLI3 : in std_logic;
HHI3 : in std_logic;
MLI0 : in std_logic;
MHI0 : in std_logic;
MSET : in std_logic;
MHI1 : in std_logic;
MLI1 : in std_logic;
MHI2 : in std_logic;
MLI2 : in std_logic;
MHI3 : in std_logic;
MLI3 : in std_logic;
ALARMOUT : out std_logic);
end component;
component INV
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of INV : component is "BLACK_BOX";
component FDC
-- synopsys translate_off
generic( INIT : bit := '0');
-- synopsys translate_on
port ( C : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute INIT of FDC : component is "0";
attribute BOX_TYPE of FDC : component is "BLACK_BOX";
begin
HH0 <= HH0_DUMMY;
HH1 <= HH1_DUMMY;
HH2 <= HH2_DUMMY;
HH3 <= HH3_DUMMY;
HL0 <= HL0_DUMMY;
HL1 <= HL1_DUMMY;
HL2 <= HL2_DUMMY;
HL3 <= HL3_DUMMY;
MH0 <= MH0_DUMMY;
MH1 <= MH1_DUMMY;
MH2 <= MH2_DUMMY;
MH3 <= MH3_DUMMY;
ML0 <= ML0_DUMMY;
ML1 <= ML1_DUMMY;
ML2 <= ML2_DUMMY;
ML3 <= ML3_DUMMY;
XLXI_1 : Plus60
port map (CLOCK=>CLOCK,
CLR=>CLR,
SET1=>SET1,
H0=>SH0,
H1=>SH1,
H2=>SH2,
H3=>SH3,
L0=>SL0,
L1=>SL1,
L2=>SL2,
L3=>SL3,
PLUS59=>PS);
XLXI_2 : Plus60
port map (CLOCK=>CLOCK,
CLR=>CLR,
SET1=>XLXN_1,
H0=>MH0_DUMMY,
H1=>MH1_DUMMY,
H2=>MH2_DUMMY,
H3=>MH3_DUMMY,
L0=>ML0_DUMMY,
L1=>ML1_DUMMY,
L2=>ML2_DUMMY,
L3=>ML3_DUMMY,
PLUS59=>PM);
XLXI_3 : Hour
port map (CLOCK=>CLOCK,
CLR=>CLR,
INPUT_M=>XLXN_4,
H0=>HH0_DUMMY,
H1=>HH1_DUMMY,
H2=>HH2_DUMMY,
H3=>HH3_DUMMY,
L0=>HL0_DUMMY,
L1=>HL1_DUMMY,
L2=>HL2_DUMMY,
L3=>HL3_DUMMY);
XLXI_4 : OR2
port map (I0=>XLXN_9,
I1=>PS,
O=>XLXN_1);
XLXI_5 : OR2
port map (I0=>XLXN_7,
I1=>PHOUR,
O=>XLXN_4);
XLXI_6 : AND2
port map (I0=>PS,
I1=>PM,
O=>XLXN_20);
XLXI_8 : OR2
port map (I0=>PAUSE,
I1=>CP,
O=>CLOCK);
XLXI_9 : alarm
port map (CLOCK=>CP,
CLR=>XLXN_13,
HHI0=>HH0_DUMMY,
HHI1=>HH1_DUMMY,
HHI2=>HH2_DUMMY,
HHI3=>HH3_DUMMY,
HLI0=>HL0_DUMMY,
HLI1=>HL1_DUMMY,
HLI2=>HL2_DUMMY,
HLI3=>HL3_DUMMY,
HSET=>XLXN_11,
MHI0=>MH0_DUMMY,
MHI1=>MH1_DUMMY,
MHI2=>MH2_DUMMY,
MHI3=>MH3_DUMMY,
MLI0=>ML0_DUMMY,
MLI1=>ML1_DUMMY,
MLI2=>ML2_DUMMY,
MLI3=>ML3_DUMMY,
MSET=>XLXN_15,
ALARMOUT=>ALARMOUT);
XLXI_10 : INV
port map (I=>HSETUP,
O=>XLXN_7);
XLXI_11 : INV
port map (I=>MSETUP,
O=>XLXN_9);
XLXI_12 : INV
port map (I=>ALMSETH,
O=>XLXN_11);
XLXI_13 : INV
port map (I=>ALMCLR,
O=>XLXN_13);
XLXI_14 : INV
port map (I=>ALMSETM,
O=>XLXN_15);
XLXI_15 : FDC
port map (C=>CLOCK,
CLR=>open,
D=>XLXN_20,
Q=>PHOUR);
end BEHAVIORAL;
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