clock.mrp

XLINX做的数字钟

Release 7.1i Map H.38
Xilinx Mapping Report File for Design 'CLOCK'

Design Information
------------------
Command Line   : D:/Xilinx/bin/nt/map.exe -ise c:\documents and
settings\administrator\桌面\数字钟\数字钟.ise -intstyle ise -p xcv100-pq240-4
-cm area -pr b -k 4 -c 100 -tx off -o CLOCK_map.ncd CLOCK.ngd CLOCK.pcf 
Target Device  : xcv100
Target Package : pq240
Target Speed   : -4
Mapper Version : virtex -- $Revision: 1.26.6.3 $
Mapped Date    : Tue Jul 01 23:12:06 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:    4
Logic Utilization:
  Number of Slice Flip Flops:        45 out of  2,400    1%
  Number of 4 input LUTs:            72 out of  2,400    3%
Logic Distribution:
    Number of occupied Slices:                          47 out of  1,200    3%
    Number of Slices containing only related logic:     47 out of     47  100%
    Number of Slices containing unrelated logic:         0 out of     47    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:        72 out of  2,400    3%
   Number of bonded IOBs:            33 out of    166   19%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            1
Total equivalent gate count for design:  804
Additional JTAG gate count for IOBs:  1,632
Peak Memory Usage:  95 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network XLXI_9/XLXI_2/XLXI_2/CEO has no load.
WARNING:LIT:374 - The above warning message base_net_load_rule is repeated 9
   more times for the following (max. 5 shown):
   XLXI_3/XLXI_1/CEO,
   XLXI_1/XLXI_2/CEO,
   XLXI_2/XLXI_2/CEO,
   XLXI_2/XLXI_1/CEO,
   XLXI_1/XLXI_1/CEO
   To see the details of these warning messages, please use the -detail switch.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXN_56 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXN_83 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
  18 block(s) removed
   4 block(s) optimized away
  19 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

Loadless block "XLXI_9/XLXI_1/XLXI_16" (AND) removed.
The signal "XLXI_9/XLXI_2/XLXI_2/TC" is sourceless and has been removed.
 Sourceless block "XLXI_9/XLXI_2/XLXI_2/I_36_99" (AND) removed.
  The signal "XLXI_9/XLXI_2/XLXI_2/CEO" is sourceless and has been removed.
The signal "XLXI_3/XLXI_1/TC" is sourceless and has been removed.
 Sourceless block "XLXI_3/XLXI_1/I_36_99" (AND) removed.
  The signal "XLXI_3/XLXI_1/CEO" is sourceless and has been removed.
The signal "XLXI_1/XLXI_2/CEO" is sourceless and has been removed.
The signal "XLXI_2/XLXI_2/CEO" is sourceless and has been removed.
The signal "XLXI_2/XLXI_1/TC" is sourceless and has been removed.
 Sourceless block "XLXI_2/XLXI_1/I_36_99" (AND) removed.
  The signal "XLXI_2/XLXI_1/CEO" is sourceless and has been removed.
The signal "XLXI_1/XLXI_1/TC" is sourceless and has been removed.
 Sourceless block "XLXI_1/XLXI_1/I_36_99" (AND) removed.
  The signal "XLXI_1/XLXI_1/CEO" is sourceless and has been removed.
The signal "XLXI_3/XLXI_2/TC" is sourceless and has been removed.
 Sourceless block "XLXI_3/XLXI_2/I_36_99" (AND) removed.
  The signal "XLXI_3/XLXI_2/CEO" is sourceless and has been removed.
The signal "XLXI_9/XLXI_1/XLXI_2/CEO" is sourceless and has been removed.
The signal "XLXI_9/XLXI_2/XLXI_1/TC" is sourceless and has been removed.
 Sourceless block "XLXI_9/XLXI_2/XLXI_1/I_36_99" (AND) removed.
  The signal "XLXI_9/XLXI_2/XLXI_1/CEO" is sourceless and has been removed.
The signal "XLXI_9/XLXI_1/XLXI_1/TC" is sourceless and has been removed.
 Sourceless block "XLXI_9/XLXI_1/XLXI_1/I_36_99" (AND) removed.
  The signal "XLXI_9/XLXI_1/XLXI_1/CEO" is sourceless and has been removed.

The trimmed logic reported below is either:
   1. part of a cycle
   2. part of disabled logic
   3. a side-effect of other trimmed logic

The signal "XLXN_84" is unused and has been removed.
The signal "XLXN_55" is unused and has been removed.
Unused block "XLXI_1/XLXI_1/I_36_105" (AND) removed.
Unused block "XLXI_1/XLXI_2/I_36_99" (AND) removed.
Unused block "XLXI_2/XLXI_1/I_36_105" (AND) removed.
Unused block "XLXI_2/XLXI_2/I_36_99" (AND) removed.
Unused block "XLXI_3/XLXI_1/I_36_105" (AND) removed.
Unused block "XLXI_3/XLXI_2/I_36_105" (AND) removed.
Unused block "XLXI_9/XLXI_1/XLXI_1/I_36_105" (AND) removed.
Unused block "XLXI_9/XLXI_1/XLXI_2/I_36_99" (AND) removed.
Unused block "XLXI_9/XLXI_2/XLXI_1/I_36_105" (AND) removed.
Unused block "XLXI_9/XLXI_2/XLXI_2/I_36_105" (AND) removed.

Optimized Block(s):
TYPE 		BLOCK
VCC 		XLXI_21
VCC 		XLXI_30
VCC 		XLXI_9/XLXI_30/I_36_107
GND 		XLXI_9/XLXI_30/I_36_109

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| CLOCK                              | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| ALARMOUT                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| ALMCLR                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| ALMSETH                            | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| ALMSETM                            | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| CLR                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| HALARM                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| HH0                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| HH1                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| HH2                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| HH3                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| HL0                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| HL1                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| HL2                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| HL3                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| HSETUP                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| MH0                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| MH1                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| MH2                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| MH3                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| ML0                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| ML1                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| ML2                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| ML3                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| MSETUP                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| SET1                               | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| SH0                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| SH1                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| SH2                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| SH3                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| SL0                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| SL1                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| SL2                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| SL3                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------
XLXI_9_XLXI_30_0                        
XLXI_9_XLXI_2_XLXI_2_1                  
XLXI_9_XLXI_2_XLXI_1_0                  
XLXI_9_XLXI_1_XLXI_2_1                  
XLXI_9_XLXI_1_XLXI_1_0                  
XLXI_3_XLXI_2_1                         
XLXI_3_XLXI_1_0                         
XLXI_2_XLXI_2_1                         
XLXI_2_XLXI_1_0                         
XLXI_1_XLXI_2_1                         
XLXI_1_XLXI_1_0                         

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
--------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 34
Number of Equivalent Gates for Design = 804
Number of RPM Macros = 1
Number of Hard Macros = 0
PCI IOBs = 0
PCI LOGICs = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
DLLs = 0
GCLKIOBs = 1
GCLKs = 1
Block RAMs = 0
TBUFs = 0
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 10
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 0
IOB Flip Flops = 0
Unbonded IOBs = 0
Bonded IOBs = 33
XORs = 0
CARRY_INITs = 2
CARRY_SKIPs = 0
CARRY_MUXes = 4
Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MULT_ANDs = 0
MUXF5s + MUXF6s = 0
4 input LUTs used as Route-Thrus = 0
4 input LUTs = 72
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 10
Slice Flip Flops = 45
Slices = 47
F6 Muxes = 0
F5 Muxes = 0
Number of LUT signals with 4 loads = 5
Number of LUT signals with 3 loads = 0
Number of LUT signals with 2 loads = 0
Number of LUT signals with 1 load = 63
NGM Average fanout of LUT = 1.61
NGM Maximum fanout of LUT = 9
NGM Average fanin for LUT = 3.0694
Number of LUT symbols = 72