testclock1.vhw

XLINX做的数字钟

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1i
--  \   \         Application : ISE Foundation
--  /   /         Filename : testclock1.vhw
-- /___/   /\     Timestamp : Sat Jun 21 20:12:03 2008
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: testclock1
--Device: Xilinx
--

library UNISIM;
use UNISIM.Vcomponents.ALL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testclock1 IS
END testclock1;

ARCHITECTURE testbench_arch OF testclock1 IS
    COMPONENT CLOCK
        PORT (
            ALMCLR : In std_logic;
            ALMSETH : In std_logic;
            ALMSETM : In std_logic;
            CLR : In std_logic;
            CP : In std_logic;
            HSETUP : In std_logic;
            MSETUP : In std_logic;
            PAUSE : In std_logic;
            SET1 : In std_logic;
            ALARMOUT : Out std_logic;
            HH0 : Out std_logic;
            HH1 : Out std_logic;
            HH2 : Out std_logic;
            HH3 : Out std_logic;
            HL0 : Out std_logic;
            HL1 : Out std_logic;
            HL2 : Out std_logic;
            HL3 : Out std_logic;
            MH0 : Out std_logic;
            MH1 : Out std_logic;
            MH2 : Out std_logic;
            MH3 : Out std_logic;
            ML0 : Out std_logic;
            ML1 : Out std_logic;
            ML2 : Out std_logic;
            ML3 : Out std_logic;
            SH0 : Out std_logic;
            SH1 : Out std_logic;
            SH2 : Out std_logic;
            SH3 : Out std_logic;
            SL0 : Out std_logic;
            SL1 : Out std_logic;
            SL2 : Out std_logic;
            SL3 : Out std_logic
        );
    END COMPONENT;

    SIGNAL ALMCLR : std_logic := '1';
    SIGNAL ALMSETH : std_logic := '0';
    SIGNAL ALMSETM : std_logic := '0';
    SIGNAL CLR : std_logic := '1';
    SIGNAL CP : std_logic := '0';
    SIGNAL HSETUP : std_logic := '0';
    SIGNAL MSETUP : std_logic := '0';
    SIGNAL PAUSE : std_logic := '1';
    SIGNAL SET1 : std_logic := '1';
    SIGNAL ALARMOUT : std_logic := '0';
    SIGNAL HH0 : std_logic := '0';
    SIGNAL HH1 : std_logic := '0';
    SIGNAL HH2 : std_logic := '0';
    SIGNAL HH3 : std_logic := '0';
    SIGNAL HL0 : std_logic := '0';
    SIGNAL HL1 : std_logic := '0';
    SIGNAL HL2 : std_logic := '0';
    SIGNAL HL3 : std_logic := '0';
    SIGNAL MH0 : std_logic := '0';
    SIGNAL MH1 : std_logic := '0';
    SIGNAL MH2 : std_logic := '0';
    SIGNAL MH3 : std_logic := '0';
    SIGNAL ML0 : std_logic := '0';
    SIGNAL ML1 : std_logic := '0';
    SIGNAL ML2 : std_logic := '0';
    SIGNAL ML3 : std_logic := '0';
    SIGNAL SH0 : std_logic := '0';
    SIGNAL SH1 : std_logic := '0';
    SIGNAL SH2 : std_logic := '0';
    SIGNAL SH3 : std_logic := '0';
    SIGNAL SL0 : std_logic := '0';
    SIGNAL SL1 : std_logic := '0';
    SIGNAL SL2 : std_logic := '0';
    SIGNAL SL3 : std_logic := '0';

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 200 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : CLOCK
        PORT MAP (
            ALMCLR => ALMCLR,
            ALMSETH => ALMSETH,
            ALMSETM => ALMSETM,
            CLR => CLR,
            CP => CP,
            HSETUP => HSETUP,
            MSETUP => MSETUP,
            PAUSE => PAUSE,
            SET1 => SET1,
            ALARMOUT => ALARMOUT,
            HH0 => HH0,
            HH1 => HH1,
            HH2 => HH2,
            HH3 => HH3,
            HL0 => HL0,
            HL1 => HL1,
            HL2 => HL2,
            HL3 => HL3,
            MH0 => MH0,
            MH1 => MH1,
            MH2 => MH2,
            MH3 => MH3,
            ML0 => ML0,
            ML1 => ML1,
            ML2 => ML2,
            ML3 => ML3,
            SH0 => SH0,
            SH1 => SH1,
            SH2 => SH2,
            SH3 => SH3,
            SL0 => SL0,
            SL1 => SL1,
            SL2 => SL2,
            SL3 => SL3
        );

        PROCESS    -- clock process for CP
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                CP <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                CP <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS
            PROCEDURE CHECK_ALARMOUT(
                next_ALARMOUT : std_logic;
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (ALARMOUT /= next_ALARMOUT) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns ALARMOUT="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ALARMOUT);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_ALARMOUT);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            PROCEDURE CHECK_HH0(
                next_HH0 : std_logic;
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (HH0 /= next_HH0) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns HH0="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, HH0);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_HH0);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            PROCEDURE CHECK_HH1(
                next_HH1 : std_logic;
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (HH1 /= next_HH1) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns HH1="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, HH1);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_HH1);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            PROCEDURE CHECK_HH2(
                next_HH2 : std_logic;
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (HH2 /= next_HH2) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns HH2="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, HH2);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_HH2);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            PROCEDURE CHECK_HH3(
                next_HH3 : std_logic;
                TX_TIME : INTEGER
            ) IS