de2_default.hier_info

The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i

SRAM_ADDR[5] <= addr_reg[5].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[6] <= addr_reg[6].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[7] <= addr_reg[7].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[8] <= addr_reg[8].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[9] <= addr_reg[9].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[10] <= addr_reg[10].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[11] <= addr_reg[11].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[12] <= addr_reg[12].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[13] <= addr_reg[13].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[14] <= addr_reg[14].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[15] <= addr_reg[15].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[16] <= addr_reg[16].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[17] <= addr_reg[17].DB_MAX_OUTPUT_PORT_TYPE
SRAM_UB_N <= <GND>
SRAM_LB_N <= <GND>
SRAM_WE_N <= we.DB_MAX_OUTPUT_PORT_TYPE
SRAM_CE_N <= <GND>
SRAM_OE_N <= <GND>
OTG_DATA[0] <= OTG_DATA~31
OTG_DATA[1] <= OTG_DATA~30
OTG_DATA[2] <= OTG_DATA~29
OTG_DATA[3] <= OTG_DATA~28
OTG_DATA[4] <= OTG_DATA~27
OTG_DATA[5] <= OTG_DATA~26
OTG_DATA[6] <= OTG_DATA~25
OTG_DATA[7] <= OTG_DATA~24
OTG_DATA[8] <= OTG_DATA~23
OTG_DATA[9] <= OTG_DATA~22
OTG_DATA[10] <= OTG_DATA~21
OTG_DATA[11] <= OTG_DATA~20
OTG_DATA[12] <= OTG_DATA~19
OTG_DATA[13] <= OTG_DATA~18
OTG_DATA[14] <= OTG_DATA~17
OTG_DATA[15] <= OTG_DATA~16
OTG_ADDR[0] <= <GND>
OTG_ADDR[1] <= <GND>
OTG_CS_N <= <GND>
OTG_RD_N <= <GND>
OTG_WR_N <= <GND>
OTG_RST_N <= <GND>
OTG_FSPEED <= <GND>
OTG_LSPEED <= <GND>
OTG_INT0 => ~NO_FANOUT~
OTG_INT1 => ~NO_FANOUT~
OTG_DREQ0 => ~NO_FANOUT~
OTG_DREQ1 => ~NO_FANOUT~
OTG_DACK0_N <= <GND>
OTG_DACK1_N <= <GND>
LCD_ON <= <GND>
LCD_BLON <= <GND>
LCD_RW <= <GND>
LCD_EN <= <GND>
LCD_RS <= <GND>
LCD_DATA[0] <= <UNC>
LCD_DATA[1] <= <UNC>
LCD_DATA[2] <= <UNC>
LCD_DATA[3] <= <UNC>
LCD_DATA[4] <= <UNC>
LCD_DATA[5] <= <UNC>
LCD_DATA[6] <= <UNC>
LCD_DATA[7] <= <UNC>
SD_DAT <= SD_DAT~0
SD_DAT3 <= <UNC>
SD_CMD <= <UNC>
SD_CLK <= <GND>
TDI => ~NO_FANOUT~
TCK => ~NO_FANOUT~
TCS => ~NO_FANOUT~
TDO <= <GND>
I2C_SDAT <= <UNC>
I2C_SCLK <= <GND>
PS2_DAT => ~NO_FANOUT~
PS2_CLK => ~NO_FANOUT~
VGA_CLK <= VGA_Audio_PLL:p1.c2
VGA_HS <= VGA_Controller:u1.oVGA_H_SYNC
VGA_VS <= VGA_Controller:u1.oVGA_V_SYNC
VGA_BLANK <= VGA_Controller:u1.oVGA_BLANK
VGA_SYNC <= VGA_Controller:u1.oVGA_SYNC
VGA_R[0] <= VGA_Controller:u1.oVGA_R
VGA_R[1] <= VGA_Controller:u1.oVGA_R
VGA_R[2] <= VGA_Controller:u1.oVGA_R
VGA_R[3] <= VGA_Controller:u1.oVGA_R
VGA_R[4] <= VGA_Controller:u1.oVGA_R
VGA_R[5] <= VGA_Controller:u1.oVGA_R
VGA_R[6] <= VGA_Controller:u1.oVGA_R
VGA_R[7] <= VGA_Controller:u1.oVGA_R
VGA_R[8] <= VGA_Controller:u1.oVGA_R
VGA_R[9] <= VGA_Controller:u1.oVGA_R
VGA_G[0] <= VGA_Controller:u1.oVGA_G
VGA_G[1] <= VGA_Controller:u1.oVGA_G
VGA_G[2] <= VGA_Controller:u1.oVGA_G
VGA_G[3] <= VGA_Controller:u1.oVGA_G
VGA_G[4] <= VGA_Controller:u1.oVGA_G
VGA_G[5] <= VGA_Controller:u1.oVGA_G
VGA_G[6] <= VGA_Controller:u1.oVGA_G
VGA_G[7] <= VGA_Controller:u1.oVGA_G
VGA_G[8] <= VGA_Controller:u1.oVGA_G
VGA_G[9] <= VGA_Controller:u1.oVGA_G
VGA_B[0] <= VGA_Controller:u1.oVGA_B
VGA_B[1] <= VGA_Controller:u1.oVGA_B
VGA_B[2] <= VGA_Controller:u1.oVGA_B
VGA_B[3] <= VGA_Controller:u1.oVGA_B
VGA_B[4] <= VGA_Controller:u1.oVGA_B
VGA_B[5] <= VGA_Controller:u1.oVGA_B
VGA_B[6] <= VGA_Controller:u1.oVGA_B
VGA_B[7] <= VGA_Controller:u1.oVGA_B
VGA_B[8] <= VGA_Controller:u1.oVGA_B
VGA_B[9] <= VGA_Controller:u1.oVGA_B
ENET_DATA[0] <= ENET_DATA~31
ENET_DATA[1] <= ENET_DATA~30
ENET_DATA[2] <= ENET_DATA~29
ENET_DATA[3] <= ENET_DATA~28
ENET_DATA[4] <= ENET_DATA~27
ENET_DATA[5] <= ENET_DATA~26
ENET_DATA[6] <= ENET_DATA~25
ENET_DATA[7] <= ENET_DATA~24
ENET_DATA[8] <= ENET_DATA~23
ENET_DATA[9] <= ENET_DATA~22
ENET_DATA[10] <= ENET_DATA~21
ENET_DATA[11] <= ENET_DATA~20
ENET_DATA[12] <= ENET_DATA~19
ENET_DATA[13] <= ENET_DATA~18
ENET_DATA[14] <= ENET_DATA~17
ENET_DATA[15] <= ENET_DATA~16
ENET_CMD <= <GND>
ENET_CS_N <= <GND>
ENET_WR_N <= <GND>
ENET_RD_N <= <GND>
ENET_RST_N <= <GND>
ENET_INT => ~NO_FANOUT~
ENET_CLK <= <GND>
AUD_ADCLRCK <= <GND>
AUD_ADCDAT => ~NO_FANOUT~
AUD_DACLRCK <= <UNC>
AUD_DACDAT <= <GND>
AUD_BCLK <= <UNC>
AUD_XCK <= <GND>
TD_DATA[0] => ~NO_FANOUT~
TD_DATA[1] => ~NO_FANOUT~
TD_DATA[2] => ~NO_FANOUT~
TD_DATA[3] => ~NO_FANOUT~
TD_DATA[4] => ~NO_FANOUT~
TD_DATA[5] => ~NO_FANOUT~
TD_DATA[6] => ~NO_FANOUT~
TD_DATA[7] => ~NO_FANOUT~
TD_HS => ~NO_FANOUT~
TD_VS => ~NO_FANOUT~
TD_RESET <= <VCC>
GPIO_0[0] <= GPIO_0~71
GPIO_0[1] <= GPIO_0~70
GPIO_0[2] <= GPIO_0~69
GPIO_0[3] <= GPIO_0~68
GPIO_0[4] <= GPIO_0~67
GPIO_0[5] <= GPIO_0~66
GPIO_0[6] <= GPIO_0~65
GPIO_0[7] <= GPIO_0~64
GPIO_0[8] <= GPIO_0~63
GPIO_0[9] <= GPIO_0~62
GPIO_0[10] <= GPIO_0~61
GPIO_0[11] <= GPIO_0~60
GPIO_0[12] <= GPIO_0~59
GPIO_0[13] <= GPIO_0~58
GPIO_0[14] <= GPIO_0~57
GPIO_0[15] <= GPIO_0~56
GPIO_0[16] <= GPIO_0~55
GPIO_0[17] <= GPIO_0~54
GPIO_0[18] <= GPIO_0~53
GPIO_0[19] <= GPIO_0~52
GPIO_0[20] <= GPIO_0~51
GPIO_0[21] <= GPIO_0~50
GPIO_0[22] <= GPIO_0~49
GPIO_0[23] <= GPIO_0~48
GPIO_0[24] <= GPIO_0~47
GPIO_0[25] <= GPIO_0~46
GPIO_0[26] <= GPIO_0~45
GPIO_0[27] <= GPIO_0~44
GPIO_0[28] <= GPIO_0~43
GPIO_0[29] <= GPIO_0~42
GPIO_0[30] <= GPIO_0~41
GPIO_0[31] <= GPIO_0~40
GPIO_0[32] <= GPIO_0~39
GPIO_0[33] <= GPIO_0~38
GPIO_0[34] <= GPIO_0~37
GPIO_0[35] <= GPIO_0~36
GPIO_1[0] <= GPIO_1~71
GPIO_1[1] <= GPIO_1~70
GPIO_1[2] <= GPIO_1~69
GPIO_1[3] <= GPIO_1~68
GPIO_1[4] <= GPIO_1~67
GPIO_1[5] <= GPIO_1~66
GPIO_1[6] <= GPIO_1~65
GPIO_1[7] <= GPIO_1~64
GPIO_1[8] <= GPIO_1~63
GPIO_1[9] <= GPIO_1~62
GPIO_1[10] <= GPIO_1~61
GPIO_1[11] <= GPIO_1~60
GPIO_1[12] <= GPIO_1~59
GPIO_1[13] <= GPIO_1~58
GPIO_1[14] <= GPIO_1~57
GPIO_1[15] <= GPIO_1~56
GPIO_1[16] <= GPIO_1~55
GPIO_1[17] <= GPIO_1~54
GPIO_1[18] <= GPIO_1~53
GPIO_1[19] <= GPIO_1~52
GPIO_1[20] <= GPIO_1~51
GPIO_1[21] <= GPIO_1~50
GPIO_1[22] <= GPIO_1~49
GPIO_1[23] <= GPIO_1~48
GPIO_1[24] <= GPIO_1~47
GPIO_1[25] <= GPIO_1~46
GPIO_1[26] <= GPIO_1~45
GPIO_1[27] <= GPIO_1~44
GPIO_1[28] <= GPIO_1~43
GPIO_1[29] <= GPIO_1~42
GPIO_1[30] <= GPIO_1~41
GPIO_1[31] <= GPIO_1~40
GPIO_1[32] <= GPIO_1~39
GPIO_1[33] <= GPIO_1~38
GPIO_1[34] <= GPIO_1~37
GPIO_1[35] <= GPIO_1~36


|DE2_Default|Reset_Delay:r0
iCLK => Cont[18].CLK
iCLK => Cont[17].CLK
iCLK => Cont[16].CLK
iCLK => Cont[15].CLK
iCLK => Cont[14].CLK
iCLK => Cont[13].CLK
iCLK => Cont[12].CLK
iCLK => Cont[11].CLK
iCLK => Cont[10].CLK
iCLK => Cont[9].CLK
iCLK => Cont[8].CLK
iCLK => Cont[7].CLK
iCLK => Cont[6].CLK
iCLK => Cont[5].CLK
iCLK => Cont[4].CLK
iCLK => Cont[3].CLK
iCLK => Cont[2].CLK
iCLK => Cont[1].CLK
iCLK => Cont[0].CLK
iCLK => oRESET~reg0.CLK
iCLK => Cont[19].CLK
oRESET <= oRESET~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DE2_Default|VGA_Audio_PLL:p1
areset => areset~0.IN1
inclk0 => sub_wire5[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
c2 <= altpll:altpll_component.clk


|DE2_Default|VGA_Audio_PLL:p1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>


|DE2_Default|VGA_Controller:u1
iCursor_RGB_EN[0] => oVGA_B~0.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~1.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~2.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~3.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~4.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~5.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~6.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~7.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~8.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~9.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~0.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~1.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~2.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~3.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~4.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~5.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~6.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~7.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~8.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~9.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~3.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~4.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~5.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~6.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~7.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~8.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~9.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~10.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~11.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~12.OUTPUTSELECT
iCursor_RGB_EN[3] => always1~8.IN1
iCursor_X[0] => Equal~0.IN53
iCursor_X[0] => add~5.IN22
iCursor_X[0] => add~7.IN22
iCursor_X[1] => Equal~0.IN52
iCursor_X[1] => add~5.IN21
iCursor_X[1] => add~7.IN21
iCursor_X[2] => add~6.IN3
iCursor_X[3] => add~6.IN2
iCursor_X[4] => add~6.IN1
iCursor_X[5] => add~6.IN8
iCursor_X[6] => add~6.IN7
iCursor_X[7] => add~6.IN0
iCursor_X[8] => add~6.IN6
iCursor_X[9] => add~6.IN5
iCursor_Y[0] => Equal~3.IN53
iCursor_Y[0] => add~8.IN22
iCursor_Y[0] => add~10.IN22
iCursor_Y[1] => add~9.IN1
iCursor_Y[2] => add~9.IN9
iCursor_Y[3] => add~9.IN8
iCursor_Y[4] => add~9.IN7
iCursor_Y[5] => add~9.IN0
iCursor_Y[6] => add~9.IN6
iCursor_Y[7] => add~9.IN5