de2_default.hier_info

The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i

|DE2_Default
CLOCK_27 => CLOCK_27~0.IN1
CLOCK_50 => CLOCK_50~0.IN1
EXT_CLOCK => ~NO_FANOUT~
KEY[0] => addr_reg~18.OUTPUTSELECT
KEY[0] => addr_reg~19.OUTPUTSELECT
KEY[0] => addr_reg~20.OUTPUTSELECT
KEY[0] => addr_reg~21.OUTPUTSELECT
KEY[0] => addr_reg~22.OUTPUTSELECT
KEY[0] => addr_reg~23.OUTPUTSELECT
KEY[0] => addr_reg~24.OUTPUTSELECT
KEY[0] => addr_reg~25.OUTPUTSELECT
KEY[0] => addr_reg~26.OUTPUTSELECT
KEY[0] => addr_reg~27.OUTPUTSELECT
KEY[0] => addr_reg~28.OUTPUTSELECT
KEY[0] => addr_reg~29.OUTPUTSELECT
KEY[0] => addr_reg~30.OUTPUTSELECT
KEY[0] => addr_reg~31.OUTPUTSELECT
KEY[0] => addr_reg~32.OUTPUTSELECT
KEY[0] => addr_reg~33.OUTPUTSELECT
KEY[0] => addr_reg~34.OUTPUTSELECT
KEY[0] => addr_reg~35.OUTPUTSELECT
KEY[0] => we~2.OUTPUTSELECT
KEY[0] => data_reg~32.OUTPUTSELECT
KEY[0] => data_reg~33.OUTPUTSELECT
KEY[0] => data_reg~34.OUTPUTSELECT
KEY[0] => data_reg~35.OUTPUTSELECT
KEY[0] => data_reg~36.OUTPUTSELECT
KEY[0] => data_reg~37.OUTPUTSELECT
KEY[0] => data_reg~38.OUTPUTSELECT
KEY[0] => data_reg~39.OUTPUTSELECT
KEY[0] => data_reg~40.OUTPUTSELECT
KEY[0] => data_reg~41.OUTPUTSELECT
KEY[0] => data_reg~42.OUTPUTSELECT
KEY[0] => data_reg~43.OUTPUTSELECT
KEY[0] => data_reg~44.OUTPUTSELECT
KEY[0] => data_reg~45.OUTPUTSELECT
KEY[0] => data_reg~46.OUTPUTSELECT
KEY[0] => data_reg~47.OUTPUTSELECT
KEY[0] => x_rand~63.OUTPUTSELECT
KEY[0] => x_rand~64.OUTPUTSELECT
KEY[0] => x_rand~65.OUTPUTSELECT
KEY[0] => x_rand~66.OUTPUTSELECT
KEY[0] => x_rand~67.OUTPUTSELECT
KEY[0] => x_rand~68.OUTPUTSELECT
KEY[0] => x_rand~69.OUTPUTSELECT
KEY[0] => x_rand~70.OUTPUTSELECT
KEY[0] => x_rand~71.OUTPUTSELECT
KEY[0] => x_rand~72.OUTPUTSELECT
KEY[0] => x_rand~73.OUTPUTSELECT
KEY[0] => x_rand~74.OUTPUTSELECT
KEY[0] => x_rand~75.OUTPUTSELECT
KEY[0] => x_rand~76.OUTPUTSELECT
KEY[0] => x_rand~77.OUTPUTSELECT
KEY[0] => x_rand~78.OUTPUTSELECT
KEY[0] => x_rand~79.OUTPUTSELECT
KEY[0] => x_rand~80.OUTPUTSELECT
KEY[0] => x_rand~81.OUTPUTSELECT
KEY[0] => x_rand~82.OUTPUTSELECT
KEY[0] => x_rand~83.OUTPUTSELECT
KEY[0] => x_rand~84.OUTPUTSELECT
KEY[0] => x_rand~85.OUTPUTSELECT
KEY[0] => x_rand~86.OUTPUTSELECT
KEY[0] => x_rand~87.OUTPUTSELECT
KEY[0] => x_rand~88.OUTPUTSELECT
KEY[0] => x_rand~89.OUTPUTSELECT
KEY[0] => x_rand~90.OUTPUTSELECT
KEY[0] => x_rand~91.OUTPUTSELECT
KEY[0] => x_rand~92.OUTPUTSELECT
KEY[0] => x_rand~93.OUTPUTSELECT
KEY[0] => y_rand~58.OUTPUTSELECT
KEY[0] => y_rand~59.OUTPUTSELECT
KEY[0] => y_rand~60.OUTPUTSELECT
KEY[0] => y_rand~61.OUTPUTSELECT
KEY[0] => y_rand~62.OUTPUTSELECT
KEY[0] => y_rand~63.OUTPUTSELECT
KEY[0] => y_rand~64.OUTPUTSELECT
KEY[0] => y_rand~65.OUTPUTSELECT
KEY[0] => y_rand~66.OUTPUTSELECT
KEY[0] => y_rand~67.OUTPUTSELECT
KEY[0] => y_rand~68.OUTPUTSELECT
KEY[0] => y_rand~69.OUTPUTSELECT
KEY[0] => y_rand~70.OUTPUTSELECT
KEY[0] => y_rand~71.OUTPUTSELECT
KEY[0] => y_rand~72.OUTPUTSELECT
KEY[0] => y_rand~73.OUTPUTSELECT
KEY[0] => y_rand~74.OUTPUTSELECT
KEY[0] => y_rand~75.OUTPUTSELECT
KEY[0] => y_rand~76.OUTPUTSELECT
KEY[0] => y_rand~77.OUTPUTSELECT
KEY[0] => y_rand~78.OUTPUTSELECT
KEY[0] => y_rand~79.OUTPUTSELECT
KEY[0] => y_rand~80.OUTPUTSELECT
KEY[0] => y_rand~81.OUTPUTSELECT
KEY[0] => y_rand~82.OUTPUTSELECT
KEY[0] => y_rand~83.OUTPUTSELECT
KEY[0] => y_rand~84.OUTPUTSELECT
KEY[0] => y_rand~85.OUTPUTSELECT
KEY[0] => y_rand~86.OUTPUTSELECT
KEY[0] => x_walker~27.OUTPUTSELECT
KEY[0] => x_walker~28.OUTPUTSELECT
KEY[0] => x_walker~29.OUTPUTSELECT
KEY[0] => x_walker~30.OUTPUTSELECT
KEY[0] => x_walker~31.OUTPUTSELECT
KEY[0] => x_walker~32.OUTPUTSELECT
KEY[0] => x_walker~33.OUTPUTSELECT
KEY[0] => x_walker~34.OUTPUTSELECT
KEY[0] => x_walker~35.OUTPUTSELECT
KEY[0] => y_walker~27.OUTPUTSELECT
KEY[0] => y_walker~28.OUTPUTSELECT
KEY[0] => y_walker~29.OUTPUTSELECT
KEY[0] => y_walker~30.OUTPUTSELECT
KEY[0] => y_walker~31.OUTPUTSELECT
KEY[0] => y_walker~32.OUTPUTSELECT
KEY[0] => y_walker~33.OUTPUTSELECT
KEY[0] => y_walker~34.OUTPUTSELECT
KEY[0] => y_walker~35.OUTPUTSELECT
KEY[0] => state~12.OUTPUTSELECT
KEY[0] => state~13.OUTPUTSELECT
KEY[0] => state~14.OUTPUTSELECT
KEY[0] => state~15.OUTPUTSELECT
KEY[0] => state~16.OUTPUTSELECT
KEY[0] => state~17.OUTPUTSELECT
KEY[0] => state~18.OUTPUTSELECT
KEY[0] => state~19.OUTPUTSELECT
KEY[0] => state~20.OUTPUTSELECT
KEY[0] => state~21.OUTPUTSELECT
KEY[0] => lock.ENA
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => always0~1.IN1
SW[0] => ~NO_FANOUT~
SW[1] => ~NO_FANOUT~
SW[2] => ~NO_FANOUT~
SW[3] => ~NO_FANOUT~
SW[4] => ~NO_FANOUT~
SW[5] => ~NO_FANOUT~
SW[6] => ~NO_FANOUT~
SW[7] => ~NO_FANOUT~
SW[8] => ~NO_FANOUT~
SW[9] => ~NO_FANOUT~
SW[10] => ~NO_FANOUT~
SW[11] => ~NO_FANOUT~
SW[12] => ~NO_FANOUT~
SW[13] => ~NO_FANOUT~
SW[14] => ~NO_FANOUT~
SW[15] => ~NO_FANOUT~
SW[16] => ~NO_FANOUT~
SW[17] => ~NO_FANOUT~
HEX0[0] <= <GND>
HEX0[1] <= <GND>
HEX0[2] <= <GND>
HEX0[3] <= <GND>
HEX0[4] <= <GND>
HEX0[5] <= <GND>
HEX0[6] <= <GND>
HEX1[0] <= <GND>
HEX1[1] <= <GND>
HEX1[2] <= <GND>
HEX1[3] <= <GND>
HEX1[4] <= <GND>
HEX1[5] <= <GND>
HEX1[6] <= <GND>
HEX2[0] <= <GND>
HEX2[1] <= <GND>
HEX2[2] <= <GND>
HEX2[3] <= <GND>
HEX2[4] <= <GND>
HEX2[5] <= <GND>
HEX2[6] <= <GND>
HEX3[0] <= <GND>
HEX3[1] <= <GND>
HEX3[2] <= <GND>
HEX3[3] <= <GND>
HEX3[4] <= <GND>
HEX3[5] <= <GND>
HEX3[6] <= <GND>
HEX4[0] <= <GND>
HEX4[1] <= <GND>
HEX4[2] <= <GND>
HEX4[3] <= <GND>
HEX4[4] <= <GND>
HEX4[5] <= <GND>
HEX4[6] <= <GND>
HEX5[0] <= <GND>
HEX5[1] <= <GND>
HEX5[2] <= <GND>
HEX5[3] <= <GND>
HEX5[4] <= <GND>
HEX5[5] <= <GND>
HEX5[6] <= <GND>
HEX6[0] <= <GND>
HEX6[1] <= <GND>
HEX6[2] <= <GND>
HEX6[3] <= <GND>
HEX6[4] <= <GND>
HEX6[5] <= <GND>
HEX6[6] <= <GND>
HEX7[0] <= <GND>
HEX7[1] <= <GND>
HEX7[2] <= <GND>
HEX7[3] <= <GND>
HEX7[4] <= <GND>
HEX7[5] <= <GND>
HEX7[6] <= <GND>
LEDG[0] <= led[0].DB_MAX_OUTPUT_PORT_TYPE
LEDG[1] <= led[1].DB_MAX_OUTPUT_PORT_TYPE
LEDG[2] <= led[2].DB_MAX_OUTPUT_PORT_TYPE
LEDG[3] <= led[3].DB_MAX_OUTPUT_PORT_TYPE
LEDG[4] <= led[4].DB_MAX_OUTPUT_PORT_TYPE
LEDG[5] <= led[5].DB_MAX_OUTPUT_PORT_TYPE
LEDG[6] <= led[6].DB_MAX_OUTPUT_PORT_TYPE
LEDG[7] <= led[7].DB_MAX_OUTPUT_PORT_TYPE
LEDG[8] <= <GND>
LEDR[0] <= <GND>
LEDR[1] <= <GND>
LEDR[2] <= <GND>
LEDR[3] <= <GND>
LEDR[4] <= <GND>
LEDR[5] <= <GND>
LEDR[6] <= <GND>
LEDR[7] <= <GND>
LEDR[8] <= <GND>
LEDR[9] <= <GND>
LEDR[10] <= <GND>
LEDR[11] <= <GND>
LEDR[12] <= <GND>
LEDR[13] <= <GND>
LEDR[14] <= <GND>
LEDR[15] <= <GND>
LEDR[16] <= <GND>
LEDR[17] <= <GND>
UART_TXD <= <GND>
UART_RXD => ~NO_FANOUT~
IRDA_TXD <= <GND>
IRDA_RXD => ~NO_FANOUT~
DRAM_DQ[0] <= DRAM_DQ~32
DRAM_DQ[1] <= DRAM_DQ~31
DRAM_DQ[2] <= DRAM_DQ~30
DRAM_DQ[3] <= DRAM_DQ~29
DRAM_DQ[4] <= DRAM_DQ~28
DRAM_DQ[5] <= DRAM_DQ~27
DRAM_DQ[6] <= DRAM_DQ~26
DRAM_DQ[7] <= DRAM_DQ~25
DRAM_DQ[8] <= DRAM_DQ~24
DRAM_DQ[9] <= DRAM_DQ~23
DRAM_DQ[10] <= DRAM_DQ~22
DRAM_DQ[11] <= DRAM_DQ~21
DRAM_DQ[12] <= DRAM_DQ~20
DRAM_DQ[13] <= DRAM_DQ~19
DRAM_DQ[14] <= DRAM_DQ~18
DRAM_DQ[15] <= DRAM_DQ~17
DRAM_ADDR[0] <= <GND>
DRAM_ADDR[1] <= <GND>
DRAM_ADDR[2] <= <GND>
DRAM_ADDR[3] <= <GND>
DRAM_ADDR[4] <= <GND>
DRAM_ADDR[5] <= <GND>
DRAM_ADDR[6] <= <GND>
DRAM_ADDR[7] <= <GND>
DRAM_ADDR[8] <= <GND>
DRAM_ADDR[9] <= <GND>
DRAM_ADDR[10] <= <GND>
DRAM_ADDR[11] <= <GND>
DRAM_LDQM <= <GND>
DRAM_UDQM <= <GND>
DRAM_WE_N <= <GND>
DRAM_CAS_N <= <GND>
DRAM_RAS_N <= <GND>
DRAM_CS_N <= <GND>
DRAM_BA_0 <= <GND>
DRAM_BA_1 <= <GND>
DRAM_CLK <= <GND>
DRAM_CKE <= <GND>
FL_DQ[0] <= FL_DQ~15
FL_DQ[1] <= FL_DQ~14
FL_DQ[2] <= FL_DQ~13
FL_DQ[3] <= FL_DQ~12
FL_DQ[4] <= FL_DQ~11
FL_DQ[5] <= FL_DQ~10
FL_DQ[6] <= FL_DQ~9
FL_DQ[7] <= FL_DQ~8
FL_ADDR[0] <= <GND>
FL_ADDR[1] <= <GND>
FL_ADDR[2] <= <GND>
FL_ADDR[3] <= <GND>
FL_ADDR[4] <= <GND>
FL_ADDR[5] <= <GND>
FL_ADDR[6] <= <GND>
FL_ADDR[7] <= <GND>
FL_ADDR[8] <= <GND>
FL_ADDR[9] <= <GND>
FL_ADDR[10] <= <GND>
FL_ADDR[11] <= <GND>
FL_ADDR[12] <= <GND>
FL_ADDR[13] <= <GND>
FL_ADDR[14] <= <GND>
FL_ADDR[15] <= <GND>
FL_ADDR[16] <= <GND>
FL_ADDR[17] <= <GND>
FL_ADDR[18] <= <GND>
FL_ADDR[19] <= <GND>
FL_ADDR[20] <= <GND>
FL_ADDR[21] <= <GND>
FL_WE_N <= <GND>
FL_RST_N <= <GND>
FL_OE_N <= <GND>
FL_CE_N <= <GND>
SRAM_DQ[0] <= SRAM_DQ~31
SRAM_DQ[0] <= SRAM_DQ~47
SRAM_DQ[1] <= SRAM_DQ~30
SRAM_DQ[1] <= SRAM_DQ~46
SRAM_DQ[2] <= SRAM_DQ~29
SRAM_DQ[2] <= SRAM_DQ~45
SRAM_DQ[3] <= SRAM_DQ~28
SRAM_DQ[3] <= SRAM_DQ~44
SRAM_DQ[4] <= SRAM_DQ~27
SRAM_DQ[4] <= VGA_Controller:u1.iBlue
SRAM_DQ[4] <= SRAM_DQ~43
SRAM_DQ[5] <= SRAM_DQ~25
SRAM_DQ[5] <= VGA_Controller:u1.iBlue
SRAM_DQ[5] <= SRAM_DQ~42
SRAM_DQ[6] <= SRAM_DQ~23
SRAM_DQ[6] <= VGA_Controller:u1.iBlue
SRAM_DQ[6] <= SRAM_DQ~41
SRAM_DQ[7] <= SRAM_DQ~21
SRAM_DQ[7] <= VGA_Controller:u1.iBlue
SRAM_DQ[7] <= SRAM_DQ~40
SRAM_DQ[8] <= SRAM_DQ~19
SRAM_DQ[8] <= VGA_Controller:u1.iGreen
SRAM_DQ[8] <= SRAM_DQ~39
SRAM_DQ[9] <= SRAM_DQ~17
SRAM_DQ[9] <= VGA_Controller:u1.iGreen
SRAM_DQ[9] <= SRAM_DQ~38
SRAM_DQ[10] <= SRAM_DQ~15
SRAM_DQ[10] <= VGA_Controller:u1.iGreen
SRAM_DQ[10] <= SRAM_DQ~37
SRAM_DQ[11] <= SRAM_DQ~13
SRAM_DQ[11] <= VGA_Controller:u1.iGreen
SRAM_DQ[11] <= SRAM_DQ~36
SRAM_DQ[12] <= SRAM_DQ~11
SRAM_DQ[12] <= VGA_Controller:u1.iRed
SRAM_DQ[12] <= SRAM_DQ~35
SRAM_DQ[13] <= SRAM_DQ~9
SRAM_DQ[13] <= VGA_Controller:u1.iRed
SRAM_DQ[13] <= SRAM_DQ~34
SRAM_DQ[14] <= SRAM_DQ~7
SRAM_DQ[14] <= VGA_Controller:u1.iRed
SRAM_DQ[14] <= SRAM_DQ~33
SRAM_DQ[15] <= SRAM_DQ~5
SRAM_DQ[15] <= VGA_Controller:u1.iRed
SRAM_DQ[15] <= SRAM_DQ~32
SRAM_ADDR[0] <= addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[1] <= addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[2] <= addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[3] <= addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[4] <= addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE