de2_default.fit.qmsg

The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.922 ns register register " "Info: Estimated most critical path is register to register delay of 4.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x_walker\[6\] 1 REG LAB_X37_Y12 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X37_Y12; Fanout = 9; REG Node = 'x_walker\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "" { x_walker[6] } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 543 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.899 ns) + CELL(0.420 ns) 1.319 ns LessThan~538 2 COMB LAB_X40_Y13 2 " "Info: 2: + IC(0.899 ns) + CELL(0.420 ns) = 1.319 ns; Loc. = LAB_X40_Y13; Fanout = 2; COMB Node = 'LessThan~538'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.319 ns" { x_walker[6] LessThan~538 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.834 ns) + CELL(0.150 ns) 2.303 ns always0~3 3 COMB LAB_X38_Y13 11 " "Info: 3: + IC(0.834 ns) + CELL(0.150 ns) = 2.303 ns; Loc. = LAB_X38_Y13; Fanout = 11; COMB Node = 'always0~3'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.984 ns" { LessThan~538 always0~3 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.618 ns) + CELL(0.420 ns) 3.341 ns Select~2536 4 COMB LAB_X38_Y12 3 " "Info: 4: + IC(0.618 ns) + CELL(0.420 ns) = 3.341 ns; Loc. = LAB_X38_Y12; Fanout = 3; COMB Node = 'Select~2536'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.038 ns" { always0~3 Select~2536 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.275 ns) 3.906 ns Select~2541 5 COMB LAB_X38_Y12 1 " "Info: 5: + IC(0.290 ns) + CELL(0.275 ns) = 3.906 ns; Loc. = LAB_X38_Y12; Fanout = 1; COMB Node = 'Select~2541'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.565 ns" { Select~2536 Select~2541 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.245 ns) 4.441 ns Select~2544 6 COMB LAB_X38_Y12 1 " "Info: 6: + IC(0.290 ns) + CELL(0.245 ns) = 4.441 ns; Loc. = LAB_X38_Y12; Fanout = 1; COMB Node = 'Select~2544'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.535 ns" { Select~2541 Select~2544 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.084 ns) 4.922 ns x_walker\[7\] 7 REG LAB_X38_Y12 9 " "Info: 7: + IC(0.397 ns) + CELL(0.084 ns) = 4.922 ns; Loc. = LAB_X38_Y12; Fanout = 9; REG Node = 'x_walker\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.481 ns" { Select~2544 x_walker[7] } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 543 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.594 ns ( 32.39 % ) " "Info: Total cell delay = 1.594 ns ( 32.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.328 ns ( 67.61 % ) " "Info: Total interconnect delay = 3.328 ns ( 67.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "4.922 ns" { x_walker[6] LessThan~538 always0~3 Select~2536 Select~2541 Select~2544 x_walker[7] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}