de2_default.fit.qmsg

The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i

{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "VGA_Audio_PLL:p1\|altpll:altpll_component\|pll clk\[2\] VGA_CLK " "Warning: PLL \"VGA_Audio_PLL:p1\|altpll:altpll_component\|pll\" output port clk\[2\] feeds output pin \"VGA_CLK\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "VGA_Audio_PLL.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/VGA_Audio_PLL.v" 60 -1 0 } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 347 -1 0 } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 261 -1 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0}