de2_default.tan.qmsg

The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register Reset_Delay:r0\|Cont\[5\] register Reset_Delay:r0\|Cont\[7\] 261.3 MHz 3.827 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 261.3 MHz between source register \"Reset_Delay:r0\|Cont\[5\]\" and destination register \"Reset_Delay:r0\|Cont\[7\]\" (period= 3.827 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.613 ns + Longest register register " "Info: + Longest register to register delay is 3.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Reset_Delay:r0\|Cont\[5\] 1 REG LCFF_X1_Y18_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y18_N23; Fanout = 3; REG Node = 'Reset_Delay:r0\|Cont\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "" { Reset_Delay:r0|Cont[5] } "NODE_NAME" } "" } } { "Reset_Delay.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/Reset_Delay.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.787 ns) + CELL(0.410 ns) 1.197 ns rtl~195 2 COMB LCCOMB_X1_Y17_N26 1 " "Info: 2: + IC(0.787 ns) + CELL(0.410 ns) = 1.197 ns; Loc. = LCCOMB_X1_Y17_N26; Fanout = 1; COMB Node = 'rtl~195'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.197 ns" { Reset_Delay:r0|Cont[5] rtl~195 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.150 ns) 1.593 ns rtl~196 3 COMB LCCOMB_X1_Y17_N28 1 " "Info: 3: + IC(0.246 ns) + CELL(0.150 ns) = 1.593 ns; Loc. = LCCOMB_X1_Y17_N28; Fanout = 1; COMB Node = 'rtl~196'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.396 ns" { rtl~195 rtl~196 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.252 ns) + CELL(0.420 ns) 2.265 ns rtl~1 4 COMB LCCOMB_X1_Y17_N22 21 " "Info: 4: + IC(0.252 ns) + CELL(0.420 ns) = 2.265 ns; Loc. = LCCOMB_X1_Y17_N22; Fanout = 21; COMB Node = 'rtl~1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.672 ns" { rtl~196 rtl~1 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.660 ns) 3.613 ns Reset_Delay:r0\|Cont\[7\] 5 REG LCFF_X1_Y18_N27 3 " "Info: 5: + IC(0.688 ns) + CELL(0.660 ns) = 3.613 ns; Loc. = LCFF_X1_Y18_N27; Fanout = 3; REG Node = 'Reset_Delay:r0\|Cont\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.348 ns" { rtl~1 Reset_Delay:r0|Cont[7] } "NODE_NAME" } "" } } { "Reset_Delay.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/Reset_Delay.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.640 ns ( 45.39 % ) " "Info: Total cell delay = 1.640 ns ( 45.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.973 ns ( 54.61 % ) " "Info: Total interconnect delay = 1.973 ns ( 54.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "3.613 ns" { Reset_Delay:r0|Cont[5] rtl~195 rtl~196 rtl~1 Reset_Delay:r0|Cont[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.613 ns" { Reset_Delay:r0|Cont[5] rtl~195 rtl~196 rtl~1 Reset_Delay:r0|Cont[7] } { 0.000ns 0.787ns 0.246ns 0.252ns 0.688ns } { 0.000ns 0.410ns 0.150ns 0.420ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.667 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.667 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 21 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 21; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.537 ns) 2.667 ns Reset_Delay:r0\|Cont\[7\] 3 REG LCFF_X1_Y18_N27 3 " "Info: 3: + IC(1.023 ns) + CELL(0.537 ns) = 2.667 ns; Loc. = LCFF_X1_Y18_N27; Fanout = 3; REG Node = 'Reset_Delay:r0\|Cont\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.560 ns" { CLOCK_50~clkctrl Reset_Delay:r0|Cont[7] } "NODE_NAME" } "" } } { "Reset_Delay.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/Reset_Delay.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 57.22 % ) " "Info: Total cell delay = 1.526 ns ( 57.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.141 ns ( 42.78 % ) " "Info: Total interconnect delay = 1.141 ns ( 42.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.667 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.667 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[7] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.667 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.667 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 21 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 21; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.537 ns) 2.667 ns Reset_Delay:r0\|Cont\[5\] 3 REG LCFF_X1_Y18_N23 3 " "Info: 3: + IC(1.023 ns) + CELL(0.537 ns) = 2.667 ns; Loc. = LCFF_X1_Y18_N23; Fanout = 3; REG Node = 'Reset_Delay:r0\|Cont\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.560 ns" { CLOCK_50~clkctrl Reset_Delay:r0|Cont[5] } "NODE_NAME" } "" } } { "Reset_Delay.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/Reset_Delay.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 57.22 % ) " "Info: Total cell delay = 1.526 ns ( 57.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.141 ns ( 42.78 % ) " "Info: Total interconnect delay = 1.141 ns ( 42.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.667 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.667 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[5] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.667 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.667 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[7] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.667 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.667 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[5] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Reset_Delay.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/Reset_Delay.v" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Reset_Delay.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/Reset_Delay.v" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "3.613 ns" { Reset_Delay:r0|Cont[5] rtl~195 rtl~196 rtl~1 Reset_Delay:r0|Cont[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.613 ns" { Reset_Delay:r0|Cont[5] rtl~195 rtl~196 rtl~1 Reset_Delay:r0|Cont[7] } { 0.000ns 0.787ns 0.246ns 0.252ns 0.688ns } { 0.000ns 0.410ns 0.150ns 0.420ns 0.660ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.667 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.667 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[7] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.667 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.667 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[5] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 register state.test5 register state.test5 391 ps " "Info: Minimum slack time is 391 ps for clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" between source register \"state.test5\" and destination register \"state.test5\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Shortest register register " "Info: + Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.test5 1 REG LCFF_X34_Y12_N25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y12_N25; Fanout = 4; REG Node = 'state.test5'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "" { state.test5 } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 301 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns state~1444 2 COMB LCCOMB_X34_Y12_N24 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X34_Y12_N24; Fanout = 1; COMB Node = 'state~1444'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.323 ns" { state.test5 state~1444 } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 301 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns state.test5 3 REG LCFF_X34_Y12_N25 4 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X34_Y12_N25; Fanout = 4; REG Node = 'state.test5'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.084 ns" { state~1444 state.test5 } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 301 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.407 ns" { state.test5 state~1444 state.test5 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "0.407 ns" { state.test5 state~1444 state.test5 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.016 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.016 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.407 ns " "Info: + Latch edge is -2.407 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 39.682 ns -2.407 ns  50 " "Info: Clock period of Destination clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" is 39.682 ns with  offset of -2.407 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.407 ns " "Info: - Launch edge is -2.407 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 39.682 ns -2.407 ns  50 " "Info: Clock period of Source clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" is 39.682 ns with  offset of -2.407 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 destination 2.596 ns + Longest register " "Info: + Longest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" to destination register is 2.596 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G11 169 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G11; Fanout = 169; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.537 ns) 2.596 ns state.test5 3 REG LCFF_X34_Y12_N25 4 " "Info: 3: + IC(0.984 ns) + CELL(0.537 ns) = 2.596 ns; Loc. = LCFF_X34_Y12_N25; Fanout = 4; REG Node = 'state.test5'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.521 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 301 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.69 % ) " "Info: Total cell delay = 0.537 ns ( 20.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.059 ns ( 79.31 % ) " "Info: Total interconnect delay = 2.059 ns ( 79.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.596 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.596 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } { 0.000ns 1.075ns 0.984ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 source 2.596 ns - Shortest register " "Info: - Shortest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" to source register is 2.596 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G11 169 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G11; Fanout = 169; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.537 ns) 2.596 ns state.test5 3 REG LCFF_X34_Y12_N25 4 " "Info: 3: + IC(0.984 ns) + CELL(0.537 ns) = 2.596 ns; Loc. = LCFF_X34_Y12_N25; Fanout = 4; REG Node = 'state.test5'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.521 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 301 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.69 % ) " "Info: Total cell delay = 0.537 ns ( 20.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.059 ns ( 79.31 % ) " "Info: Total interconnect delay = 2.059 ns ( 79.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.596 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.596 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } { 0.000ns 1.075ns 0.984ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.596 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.596 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } { 0.000ns 1.075ns 0.984ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.596 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.596 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } { 0.000ns 1.075ns 0.984ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 301 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 301 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.596 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.596 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl state.test5 } { 0.000ns 1.075ns 0.984ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.596 ns" { VGA_