de2_default.tan.qmsg

The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i

{ "Info" "ITDB_FULL_SLACK_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 register x_walker\[6\] register x_walker\[7\] 33.36 ns " "Info: Slack time is 33.36 ns for clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" between source register \"x_walker\[6\]\" and destination register \"x_walker\[7\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "158.18 MHz 6.322 ns " "Info: Fmax is 158.18 MHz (period= 6.322 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "39.469 ns + Largest register register " "Info: + Largest register to register requirement is 39.469 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "39.682 ns + " "Info: + Setup relationship between source and destination is 39.682 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 37.275 ns " "Info: + Latch edge is 37.275 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 39.682 ns -2.407 ns  50 " "Info: Clock period of Destination clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" is 39.682 ns with  offset of -2.407 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.407 ns " "Info: - Launch edge is -2.407 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 39.682 ns -2.407 ns  50 " "Info: Clock period of Source clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" is 39.682 ns with  offset of -2.407 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns + Largest " "Info: + Largest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 destination 2.603 ns + Shortest register " "Info: + Shortest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" to destination register is 2.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G11 169 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G11; Fanout = 169; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.991 ns) + CELL(0.537 ns) 2.603 ns x_walker\[7\] 3 REG LCFF_X38_Y12_N15 9 " "Info: 3: + IC(0.991 ns) + CELL(0.537 ns) = 2.603 ns; Loc. = LCFF_X38_Y12_N15; Fanout = 9; REG Node = 'x_walker\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.528 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[7] } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 543 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.63 % ) " "Info: Total cell delay = 0.537 ns ( 20.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.066 ns ( 79.37 % ) " "Info: Total interconnect delay = 2.066 ns ( 79.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.603 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.603 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[7] } { 0.000ns 1.075ns 0.991ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 source 2.602 ns - Longest register " "Info: - Longest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" to source register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G11 169 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G11; Fanout = 169; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.537 ns) 2.602 ns x_walker\[6\] 3 REG LCFF_X37_Y12_N9 9 " "Info: 3: + IC(0.990 ns) + CELL(0.537 ns) = 2.602 ns; Loc. = LCFF_X37_Y12_N9; Fanout = 9; REG Node = 'x_walker\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.527 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[6] } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 543 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.64 % ) " "Info: Total cell delay = 0.537 ns ( 20.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.065 ns ( 79.36 % ) " "Info: Total interconnect delay = 2.065 ns ( 79.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.602 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.602 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[6] } { 0.000ns 1.075ns 0.990ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.603 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.603 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[7] } { 0.000ns 1.075ns 0.991ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.602 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.602 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[6] } { 0.000ns 1.075ns 0.990ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 543 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" {  } { { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 543 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.603 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.603 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[7] } { 0.000ns 1.075ns 0.991ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.602 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.602 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[6] } { 0.000ns 1.075ns 0.990ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.109 ns - Longest register register " "Info: - Longest register to register delay is 6.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x_walker\[6\] 1 REG LCFF_X37_Y12_N9 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y12_N9; Fanout = 9; REG Node = 'x_walker\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "" { x_walker[6] } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 543 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.413 ns) 1.477 ns LessThan~538 2 COMB LCCOMB_X40_Y13_N8 2 " "Info: 2: + IC(1.064 ns) + CELL(0.413 ns) = 1.477 ns; Loc. = LCCOMB_X40_Y13_N8; Fanout = 2; COMB Node = 'LessThan~538'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.477 ns" { x_walker[6] LessThan~538 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.398 ns) 2.563 ns always0~3 3 COMB LCCOMB_X38_Y13_N2 11 " "Info: 3: + IC(0.688 ns) + CELL(0.398 ns) = 2.563 ns; Loc. = LCCOMB_X38_Y13_N2; Fanout = 11; COMB Node = 'always0~3'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.086 ns" { LessThan~538 always0~3 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.413 ns) 3.971 ns Select~2536 4 COMB LCCOMB_X38_Y12_N4 3 " "Info: 4: + IC(0.995 ns) + CELL(0.413 ns) = 3.971 ns; Loc. = LCCOMB_X38_Y12_N4; Fanout = 3; COMB Node = 'Select~2536'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "1.408 ns" { always0~3 Select~2536 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.420 ns) 4.660 ns Select~2541 5 COMB LCCOMB_X38_Y12_N6 1 " "Info: 5: + IC(0.269 ns) + CELL(0.420 ns) = 4.660 ns; Loc. = LCCOMB_X38_Y12_N6; Fanout = 1; COMB Node = 'Select~2541'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.689 ns" { Select~2536 Select~2541 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.439 ns) + CELL(0.245 ns) 5.344 ns Select~2544 6 COMB LCCOMB_X38_Y12_N8 1 " "Info: 6: + IC(0.439 ns) + CELL(0.245 ns) = 5.344 ns; Loc. = LCCOMB_X38_Y12_N8; Fanout = 1; COMB Node = 'Select~2544'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.684 ns" { Select~2541 Select~2544 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.261 ns) + CELL(0.420 ns) 6.025 ns x_walker\[7\]~feeder 7 COMB LCCOMB_X38_Y12_N14 1 " "Info: 7: + IC(0.261 ns) + CELL(0.420 ns) = 6.025 ns; Loc. = LCCOMB_X38_Y12_N14; Fanout = 1; COMB Node = 'x_walker\[7\]~feeder'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.681 ns" { Select~2544 x_walker[7]~feeder } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 543 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.109 ns x_walker\[7\] 8 REG LCFF_X38_Y12_N15 9 " "Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 6.109 ns; Loc. = LCFF_X38_Y12_N15; Fanout = 9; REG Node = 'x_walker\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "0.084 ns" { x_walker[7]~feeder x_walker[7] } "NODE_NAME" } "" } } { "DE2_Default.v" "" { Text "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.v" 543 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.393 ns ( 39.17 % ) " "Info: Total cell delay = 2.393 ns ( 39.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.716 ns ( 60.83 % ) " "Info: Total interconnect delay = 3.716 ns ( 60.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "6.109 ns" { x_walker[6] LessThan~538 always0~3 Select~2536 Select~2541 Select~2544 x_walker[7]~feeder x_walker[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.109 ns" { x_walker[6] LessThan~538 always0~3 Select~2536 Select~2541 Select~2544 x_walker[7]~feeder x_walker[7] } { 0.000ns 1.064ns 0.688ns 0.995ns 0.269ns 0.439ns 0.261ns 0.000ns } { 0.000ns 0.413ns 0.398ns 0.413ns 0.420ns 0.245ns 0.420ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.603 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.603 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[7] } { 0.000ns 1.075ns 0.991ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "2.602 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.602 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl x_walker[6] } { 0.000ns 1.075ns 0.990ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DE2_Default" "UNKNOWN" "V1" "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/db/DE2_Default.quartus_db" { Floorplan "C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/" "" "6.109 ns" { x_walker[6] LessThan~538 always0~3 Select~2536 Select~2541 Select~2544 x_walker[7]~feeder x_walker[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.109 ns" { x_walker[6] LessThan~538 always0~3 Select~2536 Select~2541 Select~2544 x_walker[7]~feeder x_walker[7] } { 0.000ns 1.064ns 0.688ns 0.995ns 0.269ns 0.439ns 0.261ns 0.000ns } { 0.000ns 0.413ns 0.398ns 0.413ns 0.420ns 0.245ns 0.420ns 0.084ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 " "Info: No valid register-to-register data paths exist for clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLOCK_27 " "Info: No valid register-to-register data paths exist for clock \"CLOCK_27\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}