altsyncram_a5h1.tdf

The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i

--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" DEVICE_FAMILY="Cyclone II" INIT_FILE="Img_DATA.hex" INIT_FILE_LAYOUT="PORT_B" LOW_POWER_MODE="AUTO" NUMWORDS_A=307200 NUMWORDS_B=38400 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="M4K" WIDTH_A=1 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=19 WIDTHAD_B=16 address_a address_b clock0 clock1 data_a q_b wren_a
--VERSION_BEGIN 5.1 cbx_altsyncram 2005:10:21:05:19:54:SJ cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_lpm_compare 2005:07:12:04:41:28:SJ cbx_lpm_decode 2005:04:28:09:28:48:SJ cbx_lpm_mux 2005:04:28:09:25:00:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ cbx_util_mgl 2005:09:13:05:23:22:SJ  VERSION_END


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FUNCTION altsyncram_4gp1 (address_a[15..0], address_b[18..0], clock0, clock1, data_a[7..0], data_b[0..0], wren_a, wren_b)
RETURNS ( q_a[7..0], q_b[0..0]);

--synthesis_resources = lut 911 M4K 67 reg 21 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_a5h1
( 
	address_a[18..0]	:	input;
	address_b[15..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	data_a[0..0]	:	input;
	q_b[7..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	altsyncram1 : altsyncram_4gp1;

BEGIN 
	altsyncram1.address_a[] = address_b[];
	altsyncram1.address_b[] = address_a[];
	altsyncram1.clock0 = clock1;
	altsyncram1.clock1 = clock0;
	altsyncram1.data_a[] = B"11111111";
	altsyncram1.data_b[] = data_a[];
	altsyncram1.wren_a = B"0";
	altsyncram1.wren_b = wren_a;
	q_b[] = altsyncram1.q_a[];
END;
--VALID FILE