📄 altsyncram_4gp1.tdf
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PORT_B_LAST_ADDRESS = 155647,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a38 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 19456,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 19967,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 155648,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 159743,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a39 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 19968,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 20479,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 159744,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 163839,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a40 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 20480,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 20991,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 163840,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 167935,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a41 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 20992,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 21503,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 167936,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 172031,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a42 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 21504,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 22015,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 172032,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 176127,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a43 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 22016,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 22527,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 176128,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 180223,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a44 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 22528,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 23039,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 180224,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 184319,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a45 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 23040,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 23551,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 184320,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 188415,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a46 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 23552,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 24063,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 188416,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 192511,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a47 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 24064,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_⌨️ 快捷键说明
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