⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 altsyncram_4gp1.tdf

📁 The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i
💻 TDF
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block2a28 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 14336,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 14847,
			PORT_A_LOGICAL_RAM_DEPTH = 38400,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 114688,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 118783,
			PORT_B_LOGICAL_RAM_DEPTH = 307200,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block2a29 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 14848,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 15359,
			PORT_A_LOGICAL_RAM_DEPTH = 38400,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 118784,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 122879,
			PORT_B_LOGICAL_RAM_DEPTH = 307200,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block2a30 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 15360,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 15871,
			PORT_A_LOGICAL_RAM_DEPTH = 38400,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 122880,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 126975,
			PORT_B_LOGICAL_RAM_DEPTH = 307200,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block2a31 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 15872,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 38400,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 126976,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 131071,
			PORT_B_LOGICAL_RAM_DEPTH = 307200,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block2a32 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 16895,
			PORT_A_LOGICAL_RAM_DEPTH = 38400,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 131072,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 135167,
			PORT_B_LOGICAL_RAM_DEPTH = 307200,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block2a33 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 16896,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 17407,
			PORT_A_LOGICAL_RAM_DEPTH = 38400,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 135168,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 139263,
			PORT_B_LOGICAL_RAM_DEPTH = 307200,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block2a34 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 17408,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 17919,
			PORT_A_LOGICAL_RAM_DEPTH = 38400,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 139264,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 143359,
			PORT_B_LOGICAL_RAM_DEPTH = 307200,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block2a35 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 17920,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 18431,
			PORT_A_LOGICAL_RAM_DEPTH = 38400,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 143360,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 147455,
			PORT_B_LOGICAL_RAM_DEPTH = 307200,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block2a36 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 18432,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 18943,
			PORT_A_LOGICAL_RAM_DEPTH = 38400,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 147456,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 151551,
			PORT_B_LOGICAL_RAM_DEPTH = 307200,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block2a37 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 18944,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 19455,
			PORT_A_LOGICAL_RAM_DEPTH = 38400,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 151552,
			PORT_B_FIRST_BIT_NUMBER = 0,
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -