📄 altsyncram_4gp1.tdf
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INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 4607,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 32768,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 36863,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a9 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 4608,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 5119,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 36864,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 40959,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a10 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 5120,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 5631,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 40960,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 45055,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a11 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 5632,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 6143,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 45056,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 49151,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a12 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 6144,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 6655,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 49152,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 53247,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a13 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 6656,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 7167,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 53248,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 57343,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a14 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 7168,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 7679,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 57344,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 61439,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a15 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 7680,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 61440,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 65535,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a16 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 8703,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 65536,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 69631,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a17 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 9,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 8,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 8704,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 9215,
PORT_A_LOGICAL_RAM_DEPTH = 38400,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 69632,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 73727,
PORT_B_LOGICAL_RAM_DEPTH = 307200,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a18 : cycloneii_ram_block
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