de2_default.map.rpt

The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i

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The equations can be found in C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/DE2_Default.map.eqn.


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; Analysis & Synthesis Messages ;
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Thu Jun 08 14:08:48 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_Default -c DE2_Default
Warning: Can't analyze file -- file C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/VGA_Controller/Img_RAM.v is missing
Info: Found 1 design units, including 1 entities, in source file VGA_Controller/VGA_Controller.v
    Info: Found entity 1: VGA_Controller
Warning: Can't analyze file -- file C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/VGA_Controller/VGA_OSD_RAM.v is missing
Warning: Can't analyze file -- file C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/VGA_Controller/VGA_PLL.v is missing
Warning: Can't analyze file -- file C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/AUDIO_DAC.v is missing
Warning (10229): Verilog HDL Expression warning at DE2_Default.v(409): truncated literal to match 29 bits
Info: Found 1 design units, including 1 entities, in source file DE2_Default.v
    Info: Found entity 1: DE2_Default
Warning: Can't analyze file -- file C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/I2C_AV_Config.v is missing
Warning: Can't analyze file -- file C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/I2C_Controller.v is missing
Warning: Can't analyze file -- file C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/LCD_Controller.v is missing
Warning: Can't analyze file -- file C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/LCD_TEST.v is missing
Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v
    Info: Found entity 1: Reset_Delay
Warning: Can't analyze file -- file C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/SEG7_LUT.v is missing
Warning: Can't analyze file -- file C:/Documents and Settings/Bruce Land/My Documents/EEdocs/ECE576/DE2/MyExamples/DE2_VGA3/SEG7_LUT_8.v is missing
Info: Found 1 design units, including 1 entities, in source file VGA_Audio_PLL.v
    Info: Found entity 1: VGA_Audio_PLL
Info: Elaborating entity "DE2_Default" for the top level hierarchy
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(171): object "EXT_CLOCK" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(175): object "SW" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(177): object "HEX0" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(178): object "HEX1" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(179): object "HEX2" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(180): object "HEX3" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(181): object "HEX4" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(182): object "HEX5" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(183): object "HEX6" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(184): object "HEX7" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(189): object "UART_TXD" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(190): object "UART_RXD" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(192): object "IRDA_TXD" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(193): object "IRDA_RXD" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(196): object "DRAM_ADDR" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(197): object "DRAM_LDQM" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(198): object "DRAM_UDQM" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(199): object "DRAM_WE_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(200): object "DRAM_CAS_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(201): object "DRAM_RAS_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(202): object "DRAM_CS_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(203): object "DRAM_BA_0" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(204): object "DRAM_BA_1" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(205): object "DRAM_CLK" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(206): object "DRAM_CKE" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(209): object "FL_ADDR" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(210): object "FL_WE_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(211): object "FL_RST_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(212): object "FL_OE_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(213): object "FL_CE_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(224): object "OTG_ADDR" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(225): object "OTG_CS_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(226): object "OTG_RD_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(227): object "OTG_WR_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(228): object "OTG_RST_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(229): object "OTG_FSPEED" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(230): object "OTG_LSPEED" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(231): object "OTG_INT0" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(232): object "OTG_INT1" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(233): object "OTG_DREQ0" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(234): object "OTG_DREQ1" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(235): object "OTG_DACK0_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(236): object "OTG_DACK1_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(238): object "LCD_DATA" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(241): object "LCD_RW" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(242): object "LCD_EN" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(243): object "LCD_RS" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(246): object "SD_DAT3" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(247): object "SD_CMD" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(248): object "SD_CLK" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(250): object "I2C_SDAT" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(251): object "I2C_SCLK" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(253): object "PS2_DAT" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(254): object "PS2_CLK" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(256): object "TDI" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(257): object "TCK" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(258): object "TCS" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(259): object "TDO" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(271): object "ENET_CMD" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(272): object "ENET_CS_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(273): object "ENET_WR_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(274): object "ENET_RD_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(275): object "ENET_RST_N" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(276): object "ENET_INT" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(277): object "ENET_CLK" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(279): object "AUD_ADCLRCK" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(280): object "AUD_ADCDAT" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(281): object "AUD_DACLRCK" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(282): object "AUD_DACDAT" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(283): object "AUD_BCLK" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(284): object "AUD_XCK" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(286): object "TD_DATA" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(287): object "TD_HS" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(288): object "TD_VS" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(305): object "seed_low_bit" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(310): object "memwait" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(328): object "mSEG7_DIG" declared but not used
Info (10035): Verilog HDL or VHDL information at DE2_Default.v(329): object "Cont" declared but not used
Warning (10230): Verilog HDL assignment warning at DE2_Default.v(500): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at DE2_Default.v(502): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at DE2_Default.v(505): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at DE2_Default.v(507): truncated value with size 32 to match size of target (9)
Warning (10034): Output port "HEX0[6]" at DE2_Default.v(177) has no driver
Warning (10034): Output port "HEX0[5]" at DE2_Default.v(177) has no driver
Warning (10034): Output port "HEX0[4]" at DE2_Default.v(177) has no driver
Warning (10034): Output port "HEX0[3]" at DE2_Default.v(177) has no driver
Warning (10034): Output port "HEX0[2]" at DE2_Default.v(177) has no driver
Warning (10034): Output port "HEX0[1]" at DE2_Default.v(177) has no driver
Warning (10034): Output port "HEX0[0]" at DE2_Default.v(177) has no driver
Warning (10034): Output port "HEX1[6]" at DE2_Default.v(178) has no driver
Warning (10034): Output port "HEX1[5]" at DE2_Default.v(178) has no driver
Warning (10034): Output port "HEX1[4]" at DE2_Default.v(178) has no driver
Warning (10034): Output port "HEX1[3]" at DE2_Default.v(178) has no driver
Warning (10034): Output port "HEX1[2]" at DE2_Default.v(178) has no driver
Warning (10034): Output port "HEX1[1]" at DE2_Default.v(178) has no driver
Warning (10034): Output port "HEX1[0]" at DE2_Default.v(178) has no driver
Warning (10034): Output port "HEX2[6]" at DE2_Default.v(179) has no driver
Warning (10034): Output port "HEX2[5]" at DE2_Default.v(179) has no driver
Warning (10034): Output port "HEX2[4]" at DE2_Default.v(179) has no driver
Warning (10034): Output port "HEX2[3]" at DE2_Default.v(179) has no driver
Warning (10034): Output port "HEX2[2]" at DE2_Default.v(179) has no driver
Warning (10034): Output port "HEX2[1]" at DE2_Default.v(179) has no driver
Warning (10034): Output port "HEX2[0]" at DE2_Default.v(179) has no driver
Warning (10034): Output port "HEX3[6]" at DE2_D