de2_default.tan.rpt

The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i

; Clock Hold: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk0'  ; 0.391 ns  ; 25.20 MHz ( period = 39.682 ns ) ; N/A                              ; state.test5                 ; state.test5                      ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                                  ;           ;                                  ;                                  ;                             ;                                  ;                                                ;                                                ; 0            ;
+---------------------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------+----------------------------------+------------------------------------------------+------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                  ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+------------+--------------+
; Clock Node Name                                ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset     ; Phase offset ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+------------+--------------+
; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 25.2 MHz         ; 0.000 ns      ; 0.000 ns     ; CLOCK_27 ; 14                    ; 15                  ; -2.407 ns  ;              ;
; VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 ;                    ; PLL output ; 25.2 MHz         ; 0.000 ns      ; 0.000 ns     ; CLOCK_27 ; 14                    ; 15                  ; -12.329 ns ;              ;
; CLOCK_27                                       ;                    ; User Pin   ; 27.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A        ;              ;
; CLOCK_50                                       ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A        ;              ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                       ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------+-------------------------------+------------------------------------------------+------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                          ; To                            ; From Clock                                     ; To Clock                                       ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------+-------------------------------+------------------------------------------------+------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 33.360 ns                               ; 158.18 MHz ( period = 6.322 ns )                    ; x_walker[6]                   ; x_walker[7]                   ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; 39.682 ns                   ; 39.469 ns                 ; 6.109 ns                ;
; 33.514 ns                               ; 162.13 MHz ( period = 6.168 ns )                    ; x_walker[7]                   ; x_walker[7]                   ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; 39.682 ns                   ; 39.468 ns                 ; 5.954 ns                ;
; 33.673 ns                               ; 166.42 MHz ( period = 6.009 ns )                    ; x_walker[4]                   ; x_walker[7]                   ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; 39.682 ns                   ; 39.455 ns                 ; 5.782 ns                ;
; 33.678 ns                               ; 166.56 MHz ( period = 6.004 ns )                    ; x_walker[2]                   ; x_walker[7]                   ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; 39.682 ns                   ; 39.456 ns                 ; 5.778 ns                ;