de2_default.fit.rpt

The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i

Fitter report for DE2_Default
Thu Jun 08 14:09:10 2006
Version 5.1 Build 176 10/26/2005 SJ Web Edition


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. Bidir Pins
 11. I/O Bank Usage
 12. All Package Pins
 13. PLL Summary
 14. PLL Usage
 15. Output Pin Default Load For Reported TCO
 16. Fitter Resource Utilization by Entity
 17. Delay Chain Summary
 18. Pad To Core Delay Chain Fanout
 19. Control Signals
 20. Global & Other Fast Signals
 21. Non-Global High Fan-Out Signals
 22. Interconnect Usage Summary
 23. LAB Logic Elements
 24. LAB-wide Signals
 25. LAB Signals Sourced
 26. LAB Signals Sourced Out
 27. LAB Distinct Inputs
 28. Advanced Data - General
 29. Advanced Data - Placement Preparation
 30. Advanced Data - Placement
 31. Advanced Data - Routing
 32. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Fitter Summary                                                               ;
+------------------------------------+-----------------------------------------+
; Fitter Status                      ; Successful - Thu Jun 08 14:09:10 2006   ;
; Quartus II Version                 ; 5.1 Build 176 10/26/2005 SJ Web Edition ;
; Revision Name                      ; DE2_Default                             ;
; Top-level Entity Name              ; DE2_Default                             ;
; Family                             ; Cyclone II                              ;
; Device                             ; EP2C35F672C6                            ;
; Timing Models                      ; Preliminary                             ;
; Total logic elements               ; 352 / 33,216 ( 1 % )                    ;
; Total registers                    ; 190                                     ;
; Total pins                         ; 425 / 475 ( 89 % )                      ;