d_latch.txt

用vhdl编写的D触发器

library ieee;
use ieee.std_logic_1164.all;
entity d_latch is
port (d,clk: in std_logic;
      q   :out std_logic);
end d_latch;
architecture behavior of d_latch is
signal d_save : std_logic;
 begin
  process(d,clk)
    begin
     if (clk='1') then
           d_save <=d;
     end if;
   q<=d_save;
  end process;
end behavior;