rec.vhd

利用fpga实现同步串口

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rec is
generic(data_no:integer:=8);	  
port(sclk:in std_logic;
synca:in std_logic;
sd1a:in std_logic;
lock0:out std_logic;
q:out std_logic_vector((data_no-1) downto 0));
end;

architecture behav of rec is
type states is (r_wait,r_receive,r_finish);
signal current_state ,next_state:states:=r_wait;
signal lock:std_logic;
signal rxd_sync:std_logic;
begin 
lock0<=lock;
pro1:process(sd1a)
begin
if sd1a='0' then rxd_sync<='0';
else rxd_sync<='1';
end if;
end process;

com:process(current_state,sclk)
variable rcnt:integer:=data_no-1;
variable q_temp:std_logic_vector((data_no-1) downto 0);
begin
if sclk'event and sclk='0' then

case current_state is
when r_wait=>
lock<='0';
if synca='1' then
next_state<=r_receive;
else next_state<=r_wait;
end if;


when r_receive=>
q_temp(rcnt):=rxd_sync;

if rcnt>0 then
next_state<=r_receive;
rcnt:=rcnt-1;
else 
q_temp(0):=rxd_sync;
next_state<=r_finish;
rcnt:=data_no-1;
end if;

when r_finish=>
lock<='1';q<=q_temp;next_state<=r_wait;
when others=>next_state<=r_wait;
end case;
end if;
end process;

reg:process(sclk)
begin
if sclk'event and sclk='1' then
current_state<=next_state;
end if;
end process;

end;