crcm.vhd

crc 校验

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity crcm is                  --- ---------for crc check
port(reset1,reset2:in std_logic;
clk,hrecv,datald:in std_logic;
sdata:in std_logic_vector(11 downto 0);
datacrco:out std_logic_vector(16 downto 0);
datacrci:in std_logic_vector(16 downto 0);
rdata:out std_logic_vector(11 downto 0);
datafini:out std_logic;
error0,hsend:out std_logic);
end;

architecture commm of crcm  is
constant multi_coef:std_logic_vector(5 downto 0):="110101";----multi_coef
signal cnt,rcnt:std_logic_vector(4 downto 0);
signal dtemp,sdatam,rdtemp:std_logic_vector(11 downto 0);
signal rdatacrc:std_logic_vector(16 downto 0);
signal st,rt:std_logic;
begin

process(clk)
variable crcvar:std_logic_vector(5 downto 0);
begin
if reset1='0' then st<='0';
 elsif clk'event and clk='1' then
 if (st='0' and datald='1') then dtemp<=sdata;sdatam<=sdata;cnt<=(others=>'0');
    hsend<='0';st<='1';
 elsif(st='1' and cnt<7) then cnt<=cnt+1;
  if(dtemp(11)='1') then crcvar:=dtemp(11 downto 6) xor multi_coef;dtemp<=crcvar(4 downto 0)&dtemp(5 downto 0)&'0';
  else dtemp<=dtemp(10 downto 0)&'0';end if;
elsif (st='1' and cnt=7) then datacrco<=sdatam&dtemp(11 downto 7);hsend<='1';cnt<=cnt+1;
elsif(st='1' and cnt=8) then hsend<='0';st<='0';
end if;
end if;
end process;

process(hrecv,clk)
variable rcrcvar:std_logic_vector(5 downto 0);
begin
if reset2='0' then rt<='0';
 elsif(clk'event and clk='1') then
 if(rt='0' and hrecv='1') then rdtemp<=datacrci(16 downto 5);rdatacrc<=datacrci;rcnt<=(others=>'0');
      error0<='0';rt<='1';
 elsif(rt='1' and rcnt<7) then datafini<='0';rcnt<=rcnt+1;rcrcvar:=rdtemp(11 downto 6)xor multi_coef;
  if(rdtemp(11)='1') then rdtemp<=rcrcvar(4 downto 0)&rdtemp(5 downto 0)&'0';
  else rdtemp<=rdtemp(10 downto 0)&'0';
  end if;
elsif(rt='1' and rcnt=7)then datafini<='1';rdata<=rdatacrc(16 downto 5);rt<='0';
  if(rdatacrc(4 downto 0)/=rdtemp(11 downto 7)) then error0<='1';end if;
end if;
end if;
end process;


end;