chuanbingvhdl.vhd

由于计算机中大部分器件使用的是串行

--八位移位寄存器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG8 IS
  PORT(D,CLK:IN STD_LOGIC;
	       Q:OUT STD_LOGIC_VECTOR(1 TO 8));
END REG8;
ARCHITECTURE REG OF REG8 IS
  COMPONENT DFF
    PORT(D,CLK:IN STD_LOGIC;
             Q:OUT STD_LOGIC);
  END COMPONENT;
  SIGNAL Z:STD_LOGIC_VECTOR(1 TO 9);
  BEGIN
    DFF7:FOR i IN 8 TO 1 GENERATE
		DFFX:DFF PORT MAP(Z(i),CLK,Z(i+1));
    END GENERATE;
  --DFF1:DFF PORT MAP(D,CLK,Z(1));
  Z(1)<=D;
  --Q<=Z;
  PROCESS(Z)
  BEGIN
  FOR i IN 1 TO 8 LOOP
    Q(i)<=Z(i);
  END LOOP;
  END PROCESS;
END REG;

--输入输出控制信号的产生
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CTR IS
  PORT(ONE3,ZERO3,CLK:IN STD_LOGIC;
	               BE:OUT STD_LOGIC);
END CTR;
ARCHITECTURE BEG OF CTR IS
  COMPONENT DFF
    PORT(D,CLK:IN STD_LOGIC;
             Q:OUT STD_LOGIC);
  END COMPONENT;
  SIGNAL Z,Q:STD_LOGIC;
BEGIN
  Z<=(NOT Q AND ONE3) OR (Q AND NOT ZERO3);
  DFF1:DFF PORT MAP(Z,CLK,Q);
  BE<=Q;
END BEG;

--六位计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COUNT6 IS
  PORT(    BE,CLK:IN STD_LOGIC;
	  THIRD,EIGHT:OUT STD_LOGIC);
END COUNT6;
ARCHITECTURE SIX OF COUNT6 IS
  COMPONENT DFF
    PORT(D,CLK:IN STD_LOGIC;
             Q:OUT STD_LOGIC);
  END COMPONENT;
  SIGNAL D,Q:STD_LOGIC_VECTOR(0 TO 2);
BEGIN
  D(0)<=BE AND NOT Q(0);
  DFF1:DFF PORT MAP(D(0),CLK,Q(0));
  D(1)<=BE AND (Q(1) XOR Q(0));
  DFF2:DFF PORT MAP(D(1),CLK,Q(1));
  D(2)<=BE AND (Q(2) XOR (Q(1) AND Q(0)));
  DFF3:DFF PORT MAP(D(2),CLK,Q(2));

  THIRD<=NOT Q(2) AND Q(1) AND Q(0);
  --THIRD<=NOT Q(2) AND Q(1) AND NOT Q(0);
  --EIGHT<=Q(2) AND Q(1) AND Q(0);
  EIGHT<=BE AND NOT Q(2) AND NOT Q(1) AND NOT Q(0);
END SIX;

--输出控制
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY OUTP8 IS
  PORT(EN:IN STD_LOGIC;
	  IN8:IN STD_LOGIC_VECTOR(1 TO 8);
	 OUT8:OUT STD_LOGIC_VECTOR(1 TO 8));
END OUTP8;
ARCHITECTURE OU OF OUTP8 IS
  COMPONENT TRI
    PORT(A_IN,OE:IN STD_LOGIC;
           A_OUT:OUT STD_LOGIC);
  END COMPONENT;
BEGIN
   CTR:FOR i IN 1 TO 8 GENERATE
		TRIX:TRI PORT MAP(IN8(i),EN,OUT8(i));
       END GENERATE;
END OU;

--主实体
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CHUANBINGVHDL IS
  PORT(X,CLK:IN STD_LOGIC;
OUTOUT,THR,EIG:OUT STD_LOGIC;
          BE:OUT STD_LOGIC;
	OUTPUT8:OUT STD_LOGIC_VECTOR(1 TO 8));
END CHUANBINGVHDL;
ARCHITECTURE ZHU OF CHUANBINGVHDL IS
  COMPONENT DFF
    PORT(D,CLK:IN STD_LOGIC;
             Q:OUT STD_LOGIC);
  END COMPONENT;
  COMPONENT REG8
    PORT(D,CLK:IN STD_LOGIC;
	         Q:OUT STD_LOGIC_VECTOR(1 TO 8));
END COMPONENT;
  COMPONENT CTR
    PORT(ONE3,ZERO3,CLK:IN STD_LOGIC;
	                 BE:OUT STD_LOGIC);
END COMPONENT;
  COMPONENT COUNT6
    PORT(    BE,CLK:IN STD_LOGIC;
	  THIRD,EIGHT:OUT STD_LOGIC);
END COMPONENT;
  COMPONENT OUTP8
    PORT(EN:IN STD_LOGIC;
		IN8:IN STD_LOGIC_VECTOR(1 TO 8);
	   OUT8:OUT STD_LOGIC_VECTOR(1 TO 8));
END COMPONENT;

  SIGNAL Z,THIRD,EIGHT,BEG,ONE3,ZERO3,EN:STD_LOGIC;
  SIGNAL CP8,O8:STD_LOGIC_VECTOR(1 TO 8);
  SIGNAL TEST3:STD_LOGIC_VECTOR(1 TO 3);
BEGIN
  Z<=X;
  REGEST:REG8 PORT MAP(Z,CLK,CP8);
         TEST3(1)<=CP8(1);
		 TEST3(2)<=CP8(2);
		 TEST3(3)<=CP8(3);
		 ONE3<=TEST3(1) AND TEST3(2) AND TEST3(3);
		 ZERO3<=THIRD AND NOT TEST3(1) AND NOT TEST3(2) AND NOT TEST3(3);
  OUTOUT<=CP8(1);
  CTROL:CTR PORT MAP(ONE3,ZERO3,CLK,BEG);
		BE<=BEG;
  COUT:COUNT6 PORT MAP(BEG,CLK,THIRD,EIGHT);
       EN<=BEG AND EIGHT;
       THR<=THIRD;
	   EIG<=EIGHT;
  OUTPUT:OUTP8 PORT MAP(EN,CP8,O8);
       OUTPUT8<=O8;
END ZHU;