mux.tdf

这是一个VHDL硬件描述语言所写的一个程序

library ieee;
use ieee.std_logic_1164.all;
entity mux is
port(i0,i1,i2,i3,a,b:in std_logic;
                   q:out std_logic);
end mux;
architecture behav of mux is
signal sel: integer;
begin
with sel select
q<=i0 when 0,
   i1 when 1,
   i2 when 2,
   i3 when 3,
'x' when others;
sel<=0 when a='0' and b='0' else
     1 when a='1' and b='0' else
     2 when a='0' and b='1' else
     3 when a='1' and b='1' else
	 4;
end behav;