ss.vhd

来自「这是一个VHDL硬件描述语言所写的一个程序」· VHDL 代码 · 共 27 行

library ieee;
USE ieee.std_logic_1164.all;
entity ss is
port (input1,input2:in std_ulogic;
      output1:out std_ulogic);
end ss;

architecture xor_arch of ss is
begin
process(input1,input2)
variable nn:std_ulogic_vector(0 to 1);

begin
 nn := input1 & input2;
 case nn is
 when "00" => output1<='0';
 when "01" => output1<='1';
 when "10" => output1<='1';
 when "11" => output1<='0';
 when others=> output1<='X';

 end case;
 end process;
 end xor_arch;