📄 or88.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity or88 is
port(
q_temp: in std_logic_vector(7 downto 0);
qout: out std_logic);
end or88;
architecture bhv of or88 is
begin
process(q_temp)
begin
qout<=q_temp(7) or q_temp(6) or q_temp(5) or q_temp(4) or q_temp(3) or q_temp(2) or q_temp(1) or q_temp(0);
end process;
end bhv;
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