codelock.tan.qmsg

实现电子密码锁的各项功能,经过编译和仿真

{ "Info" "ITDB_TH_RESULT" "Reg2:inst1\|b\[7\] q_temp\[7\] clk 0.772 ns register " "Info: th for register \"Reg2:inst1\|b\[7\]\" (data pin = \"q_temp\[7\]\", clock pin = \"clk\") is 0.772 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.649 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_169 27 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_169; Fanout = 27; CLK Node = 'clk'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "" { clk } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 0 -24 144 16 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.972 ns) + CELL(0.547 ns) 5.649 ns Reg2:inst1\|b\[7\] 2 REG LC_X1_Y17_N9 1 " "Info: 2: + IC(3.972 ns) + CELL(0.547 ns) = 5.649 ns; Loc. = LC_X1_Y17_N9; Fanout = 1; REG Node = 'Reg2:inst1\|b\[7\]'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "4.519 ns" { clk Reg2:inst1|b[7] } "NODE_NAME" } "" } } { "Reg2.vhd" "" { Text "D:/codelock/Reg2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 29.69 % " "Info: Total cell delay = 1.677 ns ( 29.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.972 ns 70.31 % " "Info: Total interconnect delay = 3.972 ns ( 70.31 % )" {  } {  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk Reg2:inst1|b[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 Reg2:inst1|b[7] } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "Reg2.vhd" "" { Text "D:/codelock/Reg2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.889 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.889 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns q_temp\[7\] 1 PIN PIN_12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_12; Fanout = 2; PIN Node = 'q_temp\[7\]'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "" { q_temp[7] } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 216 -104 64 232 "q_temp\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.521 ns) + CELL(0.238 ns) 4.889 ns Reg2:inst1\|b\[7\] 2 REG LC_X1_Y17_N9 1 " "Info: 2: + IC(3.521 ns) + CELL(0.238 ns) = 4.889 ns; Loc. = LC_X1_Y17_N9; Fanout = 1; REG Node = 'Reg2:inst1\|b\[7\]'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "3.759 ns" { q_temp[7] Reg2:inst1|b[7] } "NODE_NAME" } "" } } { "Reg2.vhd" "" { Text "D:/codelock/Reg2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.368 ns 27.98 % " "Info: Total cell delay = 1.368 ns ( 27.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.521 ns 72.02 % " "Info: Total interconnect delay = 3.521 ns ( 72.02 % )" {  } {  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "4.889 ns" { q_temp[7] Reg2:inst1|b[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.889 ns" { q_temp[7] q_temp[7]~out0 Reg2:inst1|b[7] } { 0.000ns 0.000ns 3.521ns } { 0.000ns 1.130ns 0.238ns } } }  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk Reg2:inst1|b[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 Reg2:inst1|b[7] } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "4.889 ns" { q_temp[7] Reg2:inst1|b[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.889 ns" { q_temp[7] q_temp[7]~out0 Reg2:inst1|b[7] } { 0.000ns 0.000ns 3.521ns } { 0.000ns 1.130ns 0.238ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 05 17:17:58 2007 " "Info: Processing ended: Wed Dec 05 17:17:58 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}