📄 codelock.tan.qmsg

📁 实现电子密码锁的各项功能,经过编译和仿真
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register Reg1:inst\|a\[6\] register cnt10:inst5\|cout2 302.11 MHz 3.31 ns Internal " "Info: Clock \"clk\" has Internal fmax of 302.11 MHz between source register \"Reg1:inst\|a\[6\]\" and destination register \"cnt10:inst5\|cout2\" (period= 3.31 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.108 ns + Longest register register " "Info: + Longest register to register delay is 3.108 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Reg1:inst\|a\[6\] 1 REG LC_X2_Y20_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y20_N2; Fanout = 1; REG Node = 'Reg1:inst\|a\[6\]'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "" { Reg1:inst|a[6] } "NODE_NAME" } "" } } { "Reg1.vhd" "" { Text "D:/codelock/Reg1.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.340 ns) 1.324 ns compare8:inst3\|reduce_nor~67 2 COMB LC_X2_Y17_N1 1 " "Info: 2: + IC(0.984 ns) + CELL(0.340 ns) = 1.324 ns; Loc. = LC_X2_Y17_N1; Fanout = 1; COMB Node = 'compare8:inst3\|reduce_nor~67'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "1.324 ns" { Reg1:inst|a[6] compare8:inst3|reduce_nor~67 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.454 ns) 2.121 ns compare8:inst3\|reduce_nor~68 3 COMB LC_X2_Y17_N9 8 " "Info: 3: + IC(0.343 ns) + CELL(0.454 ns) = 2.121 ns; Loc. = LC_X2_Y17_N9; Fanout = 8; COMB Node = 'compare8:inst3\|reduce_nor~68'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "0.797 ns" { compare8:inst3|reduce_nor~67 compare8:inst3|reduce_nor~68 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.467 ns) 3.108 ns cnt10:inst5\|cout2 4 REG LC_X1_Y17_N8 5 " "Info: 4: + IC(0.520 ns) + CELL(0.467 ns) = 3.108 ns; Loc. = LC_X1_Y17_N8; Fanout = 5; REG Node = 'cnt10:inst5\|cout2'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "0.987 ns" { compare8:inst3|reduce_nor~68 cnt10:inst5|cout2 } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "D:/codelock/cnt10.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.261 ns 40.57 % " "Info: Total cell delay = 1.261 ns ( 40.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.847 ns 59.43 % " "Info: Total interconnect delay = 1.847 ns ( 59.43 % )" {  } {  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "3.108 ns" { Reg1:inst|a[6] compare8:inst3|reduce_nor~67 compare8:inst3|reduce_nor~68 cnt10:inst5|cout2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.108 ns" { Reg1:inst|a[6] compare8:inst3|reduce_nor~67 compare8:inst3|reduce_nor~68 cnt10:inst5|cout2 } { 0.000ns 0.984ns 0.343ns 0.520ns } { 0.000ns 0.340ns 0.454ns 0.467ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.649 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_169 27 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_169; Fanout = 27; CLK Node = 'clk'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "" { clk } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 0 -24 144 16 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.972 ns) + CELL(0.547 ns) 5.649 ns cnt10:inst5\|cout2 2 REG LC_X1_Y17_N8 5 " "Info: 2: + IC(3.972 ns) + CELL(0.547 ns) = 5.649 ns; Loc. = LC_X1_Y17_N8; Fanout = 5; REG Node = 'cnt10:inst5\|cout2'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "4.519 ns" { clk cnt10:inst5|cout2 } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "D:/codelock/cnt10.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 29.69 % " "Info: Total cell delay = 1.677 ns ( 29.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.972 ns 70.31 % " "Info: Total interconnect delay = 3.972 ns ( 70.31 % )" {  } {  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk cnt10:inst5|cout2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 cnt10:inst5|cout2 } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.649 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_169 27 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_169; Fanout = 27; CLK Node = 'clk'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "" { clk } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 0 -24 144 16 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.972 ns) + CELL(0.547 ns) 5.649 ns Reg1:inst\|a\[6\] 2 REG LC_X2_Y20_N2 1 " "Info: 2: + IC(3.972 ns) + CELL(0.547 ns) = 5.649 ns; Loc. = LC_X2_Y20_N2; Fanout = 1; REG Node = 'Reg1:inst\|a\[6\]'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "4.519 ns" { clk Reg1:inst|a[6] } "NODE_NAME" } "" } } { "Reg1.vhd" "" { Text "D:/codelock/Reg1.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 29.69 % " "Info: Total cell delay = 1.677 ns ( 29.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.972 ns 70.31 % " "Info: Total interconnect delay = 3.972 ns ( 70.31 % )" {  } {  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk Reg1:inst|a[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 Reg1:inst|a[6] } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk cnt10:inst5|cout2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 cnt10:inst5|cout2 } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk Reg1:inst|a[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 Reg1:inst|a[6] } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "Reg1.vhd" "" { Text "D:/codelock/Reg1.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "cnt10.vhd" "" { Text "D:/codelock/cnt10.vhd" 7 -1 0 } }  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "3.108 ns" { Reg1:inst|a[6] compare8:inst3|reduce_nor~67 compare8:inst3|reduce_nor~68 cnt10:inst5|cout2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.108 ns" { Reg1:inst|a[6] compare8:inst3|reduce_nor~67 compare8:inst3|reduce_nor~68 cnt10:inst5|cout2 } { 0.000ns 0.984ns 0.343ns 0.520ns } { 0.000ns 0.340ns 0.454ns 0.467ns } } } { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk cnt10:inst5|cout2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 cnt10:inst5|cout2 } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk Reg1:inst|a[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 Reg1:inst|a[6] } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "cnt10:inst5\|c_temp\[3\] q_temp\[0\] clk 1.903 ns register " "Info: tsu for register \"cnt10:inst5\|c_temp\[3\]\" (data pin = \"q_temp\[0\]\", clock pin = \"clk\") is 1.903 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.523 ns + Longest pin register " "Info: + Longest pin to register delay is 7.523 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns q_temp\[0\] 1 PIN PIN_1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_1; Fanout = 2; PIN Node = 'q_temp\[0\]'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "" { q_temp[0] } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 216 -104 64 232 "q_temp\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.929 ns) + CELL(0.454 ns) 5.513 ns or88:inst2\|qout~46 2 COMB LC_X1_Y17_N2 1 " "Info: 2: + IC(3.929 ns) + CELL(0.454 ns) = 5.513 ns; Loc. = LC_X1_Y17_N2; Fanout = 1; COMB Node = 'or88:inst2\|qout~46'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "4.383 ns" { q_temp[0] or88:inst2|qout~46 } "NODE_NAME" } "" } } { "or88.vhd" "" { Text "D:/codelock/or88.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.454 ns) 6.293 ns inst9 3 COMB LC_X1_Y17_N6 5 " "Info: 3: + IC(0.326 ns) + CELL(0.454 ns) = 6.293 ns; Loc. = LC_X1_Y17_N6; Fanout = 5; COMB Node = 'inst9'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "0.780 ns" { or88:inst2|qout~46 inst9 } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 376 320 384 424 "inst9" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.667 ns) 7.523 ns cnt10:inst5\|c_temp\[3\] 4 REG LC_X2_Y17_N3 3 " "Info: 4: + IC(0.563 ns) + CELL(0.667 ns) = 7.523 ns; Loc. = LC_X2_Y17_N3; Fanout = 3; REG Node = 'cnt10:inst5\|c_temp\[3\]'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "1.230 ns" { inst9 cnt10:inst5|c_temp[3] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "D:/codelock/cnt10.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.705 ns 35.96 % " "Info: Total cell delay = 2.705 ns ( 35.96 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.818 ns 64.04 % " "Info: Total interconnect delay = 4.818 ns ( 64.04 % )" {  } {  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "7.523 ns" { q_temp[0] or88:inst2|qout~46 inst9 cnt10:inst5|c_temp[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.523 ns" { q_temp[0] q_temp[0]~out0 or88:inst2|qout~46 inst9 cnt10:inst5|c_temp[3] } { 0.000ns 0.000ns 3.929ns 0.326ns 0.563ns } { 0.000ns 1.130ns 0.454ns 0.454ns 0.667ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "cnt10.vhd" "" { Text "D:/codelock/cnt10.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.649 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 5.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_169 27 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_169; Fanout = 27; CLK Node = 'clk'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "" { clk } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 0 -24 144 16 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.972 ns) + CELL(0.547 ns) 5.649 ns cnt10:inst5\|c_temp\[3\] 2 REG LC_X2_Y17_N3 3 " "Info: 2: + IC(3.972 ns) + CELL(0.547 ns) = 5.649 ns; Loc. = LC_X2_Y17_N3; Fanout = 3; REG Node = 'cnt10:inst5\|c_temp\[3\]'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "4.519 ns" { clk cnt10:inst5|c_temp[3] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "D:/codelock/cnt10.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 29.69 % " "Info: Total cell delay = 1.677 ns ( 29.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.972 ns 70.31 % " "Info: Total interconnect delay = 3.972 ns ( 70.31 % )" {  } {  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk cnt10:inst5|c_temp[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 cnt10:inst5|c_temp[3] } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "7.523 ns" { q_temp[0] or88:inst2|qout~46 inst9 cnt10:inst5|c_temp[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.523 ns" { q_temp[0] q_temp[0]~out0 or88:inst2|qout~46 inst9 cnt10:inst5|c_temp[3] } { 0.000ns 0.000ns 3.929ns 0.326ns 0.563ns } { 0.000ns 1.130ns 0.454ns 0.454ns 0.667ns } } } { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk cnt10:inst5|c_temp[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 cnt10:inst5|c_temp[3] } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk fb Reg1:inst\|a\[6\] 14.707 ns register " "Info: tco from clock \"clk\" to destination pin \"fb\" through register \"Reg1:inst\|a\[6\]\" is 14.707 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.649 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_169 27 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_169; Fanout = 27; CLK Node = 'clk'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "" { clk } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 0 -24 144 16 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.972 ns) + CELL(0.547 ns) 5.649 ns Reg1:inst\|a\[6\] 2 REG LC_X2_Y20_N2 1 " "Info: 2: + IC(3.972 ns) + CELL(0.547 ns) = 5.649 ns; Loc. = LC_X2_Y20_N2; Fanout = 1; REG Node = 'Reg1:inst\|a\[6\]'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "4.519 ns" { clk Reg1:inst|a[6] } "NODE_NAME" } "" } } { "Reg1.vhd" "" { Text "D:/codelock/Reg1.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 29.69 % " "Info: Total cell delay = 1.677 ns ( 29.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.972 ns 70.31 % " "Info: Total interconnect delay = 3.972 ns ( 70.31 % )" {  } {  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk Reg1:inst|a[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 Reg1:inst|a[6] } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "Reg1.vhd" "" { Text "D:/codelock/Reg1.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.885 ns + Longest register pin " "Info: + Longest register to pin delay is 8.885 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Reg1:inst\|a\[6\] 1 REG LC_X2_Y20_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y20_N2; Fanout = 1; REG Node = 'Reg1:inst\|a\[6\]'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "" { Reg1:inst|a[6] } "NODE_NAME" } "" } } { "Reg1.vhd" "" { Text "D:/codelock/Reg1.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.340 ns) 1.324 ns compare8:inst3\|reduce_nor~67 2 COMB LC_X2_Y17_N1 1 " "Info: 2: + IC(0.984 ns) + CELL(0.340 ns) = 1.324 ns; Loc. = LC_X2_Y17_N1; Fanout = 1; COMB Node = 'compare8:inst3\|reduce_nor~67'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "1.324 ns" { Reg1:inst|a[6] compare8:inst3|reduce_nor~67 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.454 ns) 2.121 ns compare8:inst3\|reduce_nor~68 3 COMB LC_X2_Y17_N9 8 " "Info: 3: + IC(0.343 ns) + CELL(0.454 ns) = 2.121 ns; Loc. = LC_X2_Y17_N9; Fanout = 8; COMB Node = 'compare8:inst3\|reduce_nor~68'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "0.797 ns" { compare8:inst3|reduce_nor~67 compare8:inst3|reduce_nor~68 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.966 ns) + CELL(0.225 ns) 3.312 ns compare8:inst3\|fb~10 4 COMB LC_X1_Y15_N1 1 " "Info: 4: + IC(0.966 ns) + CELL(0.225 ns) = 3.312 ns; Loc. = LC_X1_Y15_N1; Fanout = 1; COMB Node = 'compare8:inst3\|fb~10'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "1.191 ns" { compare8:inst3|reduce_nor~68 compare8:inst3|fb~10 } "NODE_NAME" } "" } } { "compare8.vhd" "" { Text "D:/codelock/compare8.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.939 ns) + CELL(1.634 ns) 8.885 ns fb 5 PIN PIN_137 0 " "Info: 5: + IC(3.939 ns) + CELL(1.634 ns) = 8.885 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'fb'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.573 ns" { compare8:inst3|fb~10 fb } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 160 640 816 176 "fb" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.653 ns 29.86 % " "Info: Total cell delay = 2.653 ns ( 29.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.232 ns 70.14 % " "Info: Total interconnect delay = 6.232 ns ( 70.14 % )" {  } {  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "8.885 ns" { Reg1:inst|a[6] compare8:inst3|reduce_nor~67 compare8:inst3|reduce_nor~68 compare8:inst3|fb~10 fb } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.885 ns" { Reg1:inst|a[6] compare8:inst3|reduce_nor~67 compare8:inst3|reduce_nor~68 compare8:inst3|fb~10 fb } { 0.000ns 0.984ns 0.343ns 0.966ns 3.939ns } { 0.000ns 0.340ns 0.454ns 0.225ns 1.634ns } } }  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.649 ns" { clk Reg1:inst|a[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.649 ns" { clk clk~out0 Reg1:inst|a[6] } { 0.000ns 0.000ns 3.972ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "8.885 ns" { Reg1:inst|a[6] compare8:inst3|reduce_nor~67 compare8:inst3|reduce_nor~68 compare8:inst3|fb~10 fb } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.885 ns" { Reg1:inst|a[6] compare8:inst3|reduce_nor~67 compare8:inst3|reduce_nor~68 compare8:inst3|fb~10 fb } { 0.000ns 0.984ns 0.343ns 0.966ns 3.939ns } { 0.000ns 0.340ns 0.454ns 0.225ns 1.634ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk6 police11 9.334 ns Longest " "Info: Longest tpd from source pin \"clk6\" to destination pin \"police11\" is 9.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk6 1 PIN PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_153; Fanout = 1; PIN Node = 'clk6'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "" { clk6 } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 168 1256 1272 336 "clk6" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.884 ns) + CELL(0.225 ns) 4.239 ns inst12~76 2 COMB LC_X1_Y15_N0 1 " "Info: 2: + IC(2.884 ns) + CELL(0.225 ns) = 4.239 ns; Loc. = LC_X1_Y15_N0; Fanout = 1; COMB Node = 'inst12~76'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "3.109 ns" { clk6 inst12~76 } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 376 1280 1344 424 "inst12" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.461 ns) + CELL(1.634 ns) 9.334 ns police11 3 PIN PIN_174 0 " "Info: 3: + IC(3.461 ns) + CELL(1.634 ns) = 9.334 ns; Loc. = PIN_174; Fanout = 0; PIN Node = 'police11'" {  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "5.095 ns" { inst12~76 police11 } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 392 1344 1520 408 "police11" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.989 ns 32.02 % " "Info: Total cell delay = 2.989 ns ( 32.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.345 ns 67.98 % " "Info: Total interconnect delay = 6.345 ns ( 67.98 % )" {  } {  } 0}  } { { "D:/codelock/db/codelock_cmp.qrpt" "" { Report "D:/codelock/db/codelock_cmp.qrpt" Compiler "codelock" "UNKNOWN" "V1" "D:/codelock/db/codelock.quartus_db" { Floorplan "D:/codelock/" "" "9.334 ns" { clk6 inst12~76 police11 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.334 ns" { clk6 clk6~out0 inst12~76 police11 } { 0.000ns 0.000ns 2.884ns 3.461ns } { 0.000ns 1.130ns 0.225ns 1.634ns } } }  } 0}
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