codelock.map.qmsg

实现电子密码锁的各项功能,经过编译和仿真

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 05 17:17:45 2007 " "Info: Processing started: Wed Dec 05 17:17:45 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off codelock -c codelock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off codelock -c codelock" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Reg1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Reg1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Reg1-one " "Info: Found design unit 1: Reg1-one" {  } { { "Reg1.vhd" "" { Text "D:/codelock/Reg1.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Reg1 " "Info: Found entity 1: Reg1" {  } { { "Reg1.vhd" "" { Text "D:/codelock/Reg1.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Reg2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Reg2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Reg2-two " "Info: Found design unit 1: Reg2-two" {  } { { "Reg2.vhd" "" { Text "D:/codelock/Reg2.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Reg2 " "Info: Found entity 1: Reg2" {  } { { "Reg2.vhd" "" { Text "D:/codelock/Reg2.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "compare8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file compare8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 compare8-three " "Info: Found design unit 1: compare8-three" {  } { { "compare8.vhd" "" { Text "D:/codelock/compare8.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 compare8 " "Info: Found entity 1: compare8" {  } { { "compare8.vhd" "" { Text "D:/codelock/compare8.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "compa.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file compa.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 compa-compare_arc " "Info: Found design unit 1: compa-compare_arc" {  } { { "compa.vhd" "" { Text "D:/codelock/compa.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 compa " "Info: Found entity 1: compa" {  } { { "compa.vhd" "" { Text "D:/codelock/compa.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "or88.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file or88.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 or88-bhv " "Info: Found design unit 1: or88-bhv" {  } { { "or88.vhd" "" { Text "D:/codelock/or88.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 or88 " "Info: Found entity 1: or88" {  } { { "or88.vhd" "" { Text "D:/codelock/or88.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt30.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt30.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt30-six " "Info: Found design unit 1: cnt30-six" {  } { { "cnt30.vhd" "" { Text "D:/codelock/cnt30.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt30 " "Info: Found entity 1: cnt30" {  } { { "cnt30.vhd" "" { Text "D:/codelock/cnt30.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt10-five " "Info: Found design unit 1: cnt10-five" {  } { { "cnt10.vhd" "" { Text "D:/codelock/cnt10.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt10 " "Info: Found entity 1: cnt10" {  } { { "cnt10.vhd" "" { Text "D:/codelock/cnt10.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "codelock1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file codelock1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 codelock1 " "Info: Found entity 1: codelock1" {  } { { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "codelock1 " "Info: Elaborating entity \"codelock1\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_PIN_IGNORED" "clk4 " "Warning: Pin \"clk4\" not connected" {  } { { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 304 -120 48 320 "clk4" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "compare8 compare8:inst3 " "Info: Elaborating entity \"compare8\" for hierarchy \"compare8:inst3\"" {  } { { "codelock1.bdf" "inst3" { Schematic "D:/codelock/codelock1.bdf" { { 120 520 616 216 "inst3" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "test compare8.vhd(13) " "Warning: VHDL Process Statement warning at compare8.vhd(13): signal \"test\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "compare8.vhd" "" { Text "D:/codelock/compare8.vhd" 13 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt10 cnt10:inst5 " "Info: Elaborating entity \"cnt10\" for hierarchy \"cnt10:inst5\"" {  } { { "codelock1.bdf" "inst5" { Schematic "D:/codelock/codelock1.bdf" { { 368 512 608 464 "inst5" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "c_temp cnt10.vhd(30) " "Warning: VHDL Process Statement warning at cnt10.vhd(30): signal \"c_temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cnt10.vhd" "" { Text "D:/codelock/cnt10.vhd" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cout2_temp cnt10.vhd(31) " "Warning: VHDL Process Statement warning at cnt10.vhd(31): signal \"cout2_temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cnt10.vhd" "" { Text "D:/codelock/cnt10.vhd" 31 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "or88 or88:inst2 " "Info: Elaborating entity \"or88\" for hierarchy \"or88:inst2\"" {  } { { "codelock1.bdf" "inst2" { Schematic "D:/codelock/codelock1.bdf" { { 360 128 264 456 "inst2" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "compa compa:inst4 " "Info: Elaborating entity \"compa\" for hierarchy \"compa:inst4\"" {  } { { "codelock1.bdf" "inst4" { Schematic "D:/codelock/codelock1.bdf" { { -16 504 632 80 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reg1 Reg1:inst " "Info: Elaborating entity \"Reg1\" for hierarchy \"Reg1:inst\"" {  } { { "codelock1.bdf" "inst" { Schematic "D:/codelock/codelock1.bdf" { { 40 208 328 136 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reg2 Reg2:inst1 " "Info: Elaborating entity \"Reg2\" for hierarchy \"Reg2:inst1\"" {  } { { "codelock1.bdf" "inst1" { Schematic "D:/codelock/codelock1.bdf" { { 192 200 344 288 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt30 cnt30:inst6 " "Info: Elaborating entity \"cnt30\" for hierarchy \"cnt30:inst6\"" {  } { { "codelock1.bdf" "inst6" { Schematic "D:/codelock/codelock1.bdf" { { 368 776 872 464 "inst6" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cout3_temp cnt30.vhd(10) " "Info: (10035) Verilog HDL or VHDL information at cnt30.vhd(10): object \"cout3_temp\" declared but not used" {  } { { "cnt30.vhd" "" { Text "D:/codelock/cnt30.vhd" 10 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_temp cnt30.vhd(24) " "Warning: VHDL Process Statement warning at cnt30.vhd(24): signal \"d_temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cnt30.vhd" "" { Text "D:/codelock/cnt30.vhd" 24 0 0 } }  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "clk4 " "Warning: No output dependent on input pin \"clk4\"" {  } { { "codelock1.bdf" "" { Schematic "D:/codelock/codelock1.bdf" { { 304 -120 48 320 "clk4" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "74 " "Info: Implemented 74 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "19 " "Info: Implemented 19 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "43 " "Info: Implemented 43 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 05 17:17:48 2007 " "Info: Processing ended: Wed Dec 05 17:17:48 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}