codeloc1k.tan.qmsg

实现电子密码锁的各项功能,经过编译和仿真

{ "Info" "ITDB_TH_RESULT" "Reg2:inst1\|b\[5\] q_temp\[5\] clk2 3.531 ns register " "Info: th for register \"Reg2:inst1\|b\[5\]\" (data pin = \"q_temp\[5\]\", clock pin = \"clk2\") is 3.531 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 destination 8.561 ns + Longest register " "Info: + Longest clock path from clock \"clk2\" to destination register is 8.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk2 1 CLK PIN_173 10 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_173; Fanout = 10; CLK Node = 'clk2'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "" { clk2 } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codeloc1k/codelock1.bdf" { { 152 -32 136 168 "clk2" "" } { -8 712 744 8 "clk2" "" } { 160 120 136 240 "clk2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.884 ns) + CELL(0.547 ns) 8.561 ns Reg2:inst1\|b\[5\] 2 REG LC_X2_Y18_N2 1 " "Info: 2: + IC(6.884 ns) + CELL(0.547 ns) = 8.561 ns; Loc. = LC_X2_Y18_N2; Fanout = 1; REG Node = 'Reg2:inst1\|b\[5\]'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "7.431 ns" { clk2 Reg2:inst1|b[5] } "NODE_NAME" } "" } } { "Reg2.vhd" "" { Text "D:/codeloc1k/Reg2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 19.59 % " "Info: Total cell delay = 1.677 ns ( 19.59 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.884 ns 80.41 % " "Info: Total interconnect delay = 6.884 ns ( 80.41 % )" {  } {  } 0}  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "8.561 ns" { clk2 Reg2:inst1|b[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.561 ns" { clk2 clk2~out0 Reg2:inst1|b[5] } { 0.000ns 0.000ns 6.884ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "Reg2.vhd" "" { Text "D:/codeloc1k/Reg2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.042 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.042 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns q_temp\[5\] 1 PIN PIN_7 2 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_7; Fanout = 2; PIN Node = 'q_temp\[5\]'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "" { q_temp[5] } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codeloc1k/codelock1.bdf" { { 216 -104 64 232 "q_temp\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.823 ns) + CELL(0.089 ns) 5.042 ns Reg2:inst1\|b\[5\] 2 REG LC_X2_Y18_N2 1 " "Info: 2: + IC(3.823 ns) + CELL(0.089 ns) = 5.042 ns; Loc. = LC_X2_Y18_N2; Fanout = 1; REG Node = 'Reg2:inst1\|b\[5\]'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "3.912 ns" { q_temp[5] Reg2:inst1|b[5] } "NODE_NAME" } "" } } { "Reg2.vhd" "" { Text "D:/codeloc1k/Reg2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.219 ns 24.18 % " "Info: Total cell delay = 1.219 ns ( 24.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.823 ns 75.82 % " "Info: Total interconnect delay = 3.823 ns ( 75.82 % )" {  } {  } 0}  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "5.042 ns" { q_temp[5] Reg2:inst1|b[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.042 ns" { q_temp[5] q_temp[5]~out0 Reg2:inst1|b[5] } { 0.000ns 0.000ns 3.823ns } { 0.000ns 1.130ns 0.089ns } } }  } 0}  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "8.561 ns" { clk2 Reg2:inst1|b[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.561 ns" { clk2 clk2~out0 Reg2:inst1|b[5] } { 0.000ns 0.000ns 6.884ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "5.042 ns" { q_temp[5] Reg2:inst1|b[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.042 ns" { q_temp[5] q_temp[5]~out0 Reg2:inst1|b[5] } { 0.000ns 0.000ns 3.823ns } { 0.000ns 1.130ns 0.089ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 06 15:21:41 2007 " "Info: Processing ended: Thu Dec 06 15:21:41 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}