codeloc1k.tan.qmsg

实现电子密码锁的各项功能,经过编译和仿真

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 06 15:21:40 2007 " "Info: Processing started: Thu Dec 06 15:21:40 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off codeloc1k -c codeloc1k --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off codeloc1k -c codeloc1k --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk4 " "Info: Assuming node \"clk4\" is an undefined clock" {  } { { "codelock1.bdf" "" { Schematic "D:/codeloc1k/codelock1.bdf" { { 304 -120 48 320 "clk4" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk4" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk2 " "Info: Assuming node \"clk2\" is an undefined clock" {  } { { "codelock1.bdf" "" { Schematic "D:/codeloc1k/codelock1.bdf" { { 152 -32 136 168 "clk2" "" } { -8 712 744 8 "clk2" "" } { 160 120 136 240 "clk2" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "codelock1.bdf" "" { Schematic "D:/codeloc1k/codelock1.bdf" { { -8 -16 152 8 "clk1" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk4 register cnt30:inst6\|d_temp\[1\] register cnt30:inst6\|d_temp\[0\] 337.38 MHz 2.964 ns Internal " "Info: Clock \"clk4\" has Internal fmax of 337.38 MHz between source register \"cnt30:inst6\|d_temp\[1\]\" and destination register \"cnt30:inst6\|d_temp\[0\]\" (period= 2.964 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.762 ns + Longest register register " "Info: + Longest register to register delay is 2.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt30:inst6\|d_temp\[1\] 1 REG LC_X1_Y15_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y15_N1; Fanout = 6; REG Node = 'cnt30:inst6\|d_temp\[1\]'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "" { cnt30:inst6|d_temp[1] } "NODE_NAME" } "" } } { "cnt30.vhd" "" { Text "D:/codeloc1k/cnt30.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.418 ns) + CELL(0.454 ns) 0.872 ns cnt30:inst6\|LessThan~58 2 COMB LC_X1_Y15_N6 1 " "Info: 2: + IC(0.418 ns) + CELL(0.454 ns) = 0.872 ns; Loc. = LC_X1_Y15_N6; Fanout = 1; COMB Node = 'cnt30:inst6\|LessThan~58'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "0.872 ns" { cnt30:inst6|d_temp[1] cnt30:inst6|LessThan~58 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.527 ns) + CELL(0.340 ns) 1.739 ns cnt30:inst6\|d_temp\[4\]~4 3 COMB LC_X1_Y15_N9 5 " "Info: 3: + IC(0.527 ns) + CELL(0.340 ns) = 1.739 ns; Loc. = LC_X1_Y15_N9; Fanout = 5; COMB Node = 'cnt30:inst6\|d_temp\[4\]~4'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "0.867 ns" { cnt30:inst6|LessThan~58 cnt30:inst6|d_temp[4]~4 } "NODE_NAME" } "" } } { "cnt30.vhd" "" { Text "D:/codeloc1k/cnt30.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.356 ns) + CELL(0.667 ns) 2.762 ns cnt30:inst6\|d_temp\[0\] 4 REG LC_X1_Y15_N0 4 " "Info: 4: + IC(0.356 ns) + CELL(0.667 ns) = 2.762 ns; Loc. = LC_X1_Y15_N0; Fanout = 4; REG Node = 'cnt30:inst6\|d_temp\[0\]'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "1.023 ns" { cnt30:inst6|d_temp[4]~4 cnt30:inst6|d_temp[0] } "NODE_NAME" } "" } } { "cnt30.vhd" "" { Text "D:/codeloc1k/cnt30.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.461 ns 52.90 % " "Info: Total cell delay = 1.461 ns ( 52.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.301 ns 47.10 % " "Info: Total interconnect delay = 1.301 ns ( 47.10 % )" {  } {  } 0}  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "2.762 ns" { cnt30:inst6|d_temp[1] cnt30:inst6|LessThan~58 cnt30:inst6|d_temp[4]~4 cnt30:inst6|d_temp[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.762 ns" { cnt30:inst6|d_temp[1] cnt30:inst6|LessThan~58 cnt30:inst6|d_temp[4]~4 cnt30:inst6|d_temp[0] } { 0.000ns 0.418ns 0.527ns 0.356ns } { 0.000ns 0.454ns 0.340ns 0.667ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk4 destination 2.271 ns + Shortest register " "Info: + Shortest clock path from clock \"clk4\" to destination register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk4 1 CLK PIN_153 13 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_153; Fanout = 13; CLK Node = 'clk4'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "" { clk4 } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codeloc1k/codelock1.bdf" { { 304 -120 48 320 "clk4" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns cnt30:inst6\|d_temp\[0\] 2 REG LC_X1_Y15_N0 4 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X1_Y15_N0; Fanout = 4; REG Node = 'cnt30:inst6\|d_temp\[0\]'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "1.141 ns" { clk4 cnt30:inst6|d_temp[0] } "NODE_NAME" } "" } } { "cnt30.vhd" "" { Text "D:/codeloc1k/cnt30.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 73.84 % " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns 26.16 % " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0}  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "2.271 ns" { clk4 cnt30:inst6|d_temp[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.271 ns" { clk4 clk4~out0 cnt30:inst6|d_temp[0] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk4 source 2.271 ns - Longest register " "Info: - Longest clock path from clock \"clk4\" to source register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk4 1 CLK PIN_153 13 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_153; Fanout = 13; CLK Node = 'clk4'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "" { clk4 } "NODE_NAME" } "" } } { "codelock1.bdf" "" { Schematic "D:/codeloc1k/codelock1.bdf" { { 304 -120 48 320 "clk4" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns cnt30:inst6\|d_temp\[1\] 2 REG LC_X1_Y15_N1 6 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X1_Y15_N1; Fanout = 6; REG Node = 'cnt30:inst6\|d_temp\[1\]'" {  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "1.141 ns" { clk4 cnt30:inst6|d_temp[1] } "NODE_NAME" } "" } } { "cnt30.vhd" "" { Text "D:/codeloc1k/cnt30.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 73.84 % " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns 26.16 % " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0}  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "2.271 ns" { clk4 cnt30:inst6|d_temp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.271 ns" { clk4 clk4~out0 cnt30:inst6|d_temp[1] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "2.271 ns" { clk4 cnt30:inst6|d_temp[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.271 ns" { clk4 clk4~out0 cnt30:inst6|d_temp[0] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "2.271 ns" { clk4 cnt30:inst6|d_temp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.271 ns" { clk4 clk4~out0 cnt30:inst6|d_temp[1] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "cnt30.vhd" "" { Text "D:/codeloc1k/cnt30.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "cnt30.vhd" "" { Text "D:/codeloc1k/cnt30.vhd" 11 -1 0 } }  } 0}  } { { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "2.762 ns" { cnt30:inst6|d_temp[1] cnt30:inst6|LessThan~58 cnt30:inst6|d_temp[4]~4 cnt30:inst6|d_temp[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.762 ns" { cnt30:inst6|d_temp[1] cnt30:inst6|LessThan~58 cnt30:inst6|d_temp[4]~4 cnt30:inst6|d_temp[0] } { 0.000ns 0.418ns 0.527ns 0.356ns } { 0.000ns 0.454ns 0.340ns 0.667ns } } } { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "2.271 ns" { clk4 cnt30:inst6|d_temp[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.271 ns" { clk4 clk4~out0 cnt30:inst6|d_temp[0] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/codeloc1k/db/codeloc1k_cmp.qrpt" "" { Report "D:/codeloc1k/db/codeloc1k_cmp.qrpt" Compiler "codeloc1k" "UNKNOWN" "V1" "D:/codeloc1k/db/codeloc1k.quartus_db" { Floorplan "D:/codeloc1k/" "" "2.271 ns" { clk4 cnt30:inst6|d_temp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.271 ns" { clk4 clk4~out0 cnt30:inst6|d_temp[1] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}