codelock.map.rpt

实现电子密码锁的各项功能,经过编译和仿真

+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 43      ;
; Total combinational functions     ; 26      ;
;     -- Total 4-input functions    ; 12      ;
;     -- Total 3-input functions    ; 4       ;
;     -- Total 2-input functions    ; 5       ;
;     -- Total 1-input functions    ; 5       ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 27      ;
; Total logic cells in carry chains ; 5       ;
; I/O pins                          ; 31      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 27      ;
; Total fan-out                     ; 146     ;
; Average fan-out                   ; 1.97    ;
+-----------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------+
; |codelock1                 ; 43 (2)      ; 27           ; 0           ; 31   ; 0            ; 16 (2)       ; 17 (0)            ; 10 (0)           ; 5 (0)           ; |codelock1                ;
;    |Reg1:inst|             ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; |codelock1|Reg1:inst      ;
;    |Reg2:inst1|            ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; |codelock1|Reg2:inst1     ;
;    |cnt10:inst5|           ; 8 (8)       ; 5            ; 0           ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; |codelock1|cnt10:inst5    ;
;    |cnt30:inst6|           ; 8 (8)       ; 6            ; 0           ; 0    ; 0            ; 2 (2)        ; 1 (1)             ; 5 (5)            ; 5 (5)           ; |codelock1|cnt30:inst6    ;
;    |compare8:inst3|        ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |codelock1|compare8:inst3 ;
;    |or88:inst2|            ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |codelock1|or88:inst2     ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 27    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 11    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |codelock1|cnt10:inst5|c_temp[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/codelock/codelock.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Dec 05 17:17:45 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off codelock -c codelock
Info: Found 2 design units, including 1 entities, in source file Reg1.vhd
    Info: Found design unit 1: Reg1-one
    Info: Found entity 1: Reg1
Info: Found 2 design units, including 1 entities, in source file Reg2.vhd
    Info: Found design unit 1: Reg2-two
    Info: Found entity 1: Reg2
Info: Found 2 design units, including 1 entities, in source file compare8.vhd
    Info: Found design unit 1: compare8-three
    Info: Found entity 1: compare8
Info: Found 2 design units, including 1 entities, in source file compa.vhd
    Info: Found design unit 1: compa-compare_arc
    Info: Found entity 1: compa
Info: Found 2 design units, including 1 entities, in source file or88.vhd
    Info: Found design unit 1: or88-bhv
    Info: Found entity 1: or88
Info: Found 2 design units, including 1 entities, in source file cnt30.vhd
    Info: Found design unit 1: cnt30-six
    Info: Found entity 1: cnt30
Info: Found 2 design units, including 1 entities, in source file cnt10.vhd
    Info: Found design unit 1: cnt10-five
    Info: Found entity 1: cnt10
Info: Found 1 design units, including 1 entities, in source file codelock1.bdf
    Info: Found entity 1: codelock1
Info: Elaborating entity "codelock1" for the top level hierarchy
Warning: Pin "clk4" not connected
Info: Elaborating entity "compare8" for hierarchy "compare8:inst3"
Warning: VHDL Process Statement warning at compare8.vhd(13): signal "test" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "cnt10" for hierarchy "cnt10:inst5"
Warning: VHDL Process Statement warning at cnt10.vhd(30): signal "c_temp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cnt10.vhd(31): signal "cout2_temp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "or88" for hierarchy "or88:inst2"
Info: Elaborating entity "compa" for hierarchy "compa:inst4"
Info: Elaborating entity "Reg1" for hierarchy "Reg1:inst"
Info: Elaborating entity "Reg2" for hierarchy "Reg2:inst1"
Info: Elaborating entity "cnt30" for hierarchy "cnt30:inst6"
Info: (10035) Verilog HDL or VHDL information at cnt30.vhd(10): object "cout3_temp" declared but not used
Warning: VHDL Process Statement warning at cnt30.vhd(24): signal "d_temp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "clk4"
Info: Implemented 74 device resources after synthesis - the final resource count might be different
    Info: Implemented 19 input pins
    Info: Implemented 12 output pins
    Info: Implemented 43 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Processing ended: Wed Dec 05 17:17:48 2007
    Info: Elapsed time: 00:00:03