📄 police111.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity police111 is
port(clk7:in std_logic;
tes:in std_logic;
police11:out std_logic);
end police111;
architecture one of police111 is
begin
process(tes,clk7)
begin
if tes='1' then
police11<=clk7;
else
police11<='0';
end if;
end process;
end one;
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