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📄 codelock.map.eqn

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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--G1_cout2 is cnt10:inst5|cout2
--operation mode is normal

G1_cout2_lut_out = !E1L7 & (G1L9);
G1_cout2 = DFFEAS(G1_cout2_lut_out, clk, VCC, , inst9, , , , );


--C1_b[1] is Reg2:inst1|b[1]
--operation mode is normal

C1_b[1]_lut_out = q_temp[1];
C1_b[1] = DFFEAS(C1_b[1]_lut_out, clk, VCC, , , , , , );


--C1_b[7] is Reg2:inst1|b[7]
--operation mode is normal

C1_b[7]_lut_out = q_temp[7];
C1_b[7] = DFFEAS(C1_b[7]_lut_out, clk, VCC, , , , , , );


--B1_a[7] is Reg1:inst|a[7]
--operation mode is normal

B1_a[7]_lut_out = q[7];
B1_a[7] = DFFEAS(B1_a[7]_lut_out, clk, VCC, , , , , , );


--B1_a[1] is Reg1:inst|a[1]
--operation mode is normal

B1_a[1]_lut_out = q[1];
B1_a[1] = DFFEAS(B1_a[1]_lut_out, clk, VCC, , , , , , );


--E1L3 is compare8:inst3|reduce_nor~64
--operation mode is normal

E1L3 = C1_b[1] & B1_a[1] & (C1_b[7] $ !B1_a[7]) # !C1_b[1] & !B1_a[1] & (C1_b[7] $ !B1_a[7]);


--C1_b[0] is Reg2:inst1|b[0]
--operation mode is normal

C1_b[0]_lut_out = q_temp[0];
C1_b[0] = DFFEAS(C1_b[0]_lut_out, clk, VCC, , , , , , );


--C1_b[5] is Reg2:inst1|b[5]
--operation mode is normal

C1_b[5]_lut_out = q_temp[5];
C1_b[5] = DFFEAS(C1_b[5]_lut_out, clk, VCC, , , , , , );


--B1_a[5] is Reg1:inst|a[5]
--operation mode is normal

B1_a[5]_lut_out = q[5];
B1_a[5] = DFFEAS(B1_a[5]_lut_out, clk, VCC, , , , , , );


--B1_a[0] is Reg1:inst|a[0]
--operation mode is normal

B1_a[0]_lut_out = q[0];
B1_a[0] = DFFEAS(B1_a[0]_lut_out, clk, VCC, , , , , , );


--E1L4 is compare8:inst3|reduce_nor~65
--operation mode is normal

E1L4 = C1_b[0] & B1_a[0] & (C1_b[5] $ !B1_a[5]) # !C1_b[0] & !B1_a[0] & (C1_b[5] $ !B1_a[5]);


--C1_b[3] is Reg2:inst1|b[3]
--operation mode is normal

C1_b[3]_lut_out = q_temp[3];
C1_b[3] = DFFEAS(C1_b[3]_lut_out, clk, VCC, , , , , , );


--C1_b[4] is Reg2:inst1|b[4]
--operation mode is normal

C1_b[4]_lut_out = q_temp[4];
C1_b[4] = DFFEAS(C1_b[4]_lut_out, clk, VCC, , , , , , );


--B1_a[4] is Reg1:inst|a[4]
--operation mode is normal

B1_a[4]_lut_out = q[4];
B1_a[4] = DFFEAS(B1_a[4]_lut_out, clk, VCC, , , , , , );


--B1_a[3] is Reg1:inst|a[3]
--operation mode is normal

B1_a[3]_lut_out = q[3];
B1_a[3] = DFFEAS(B1_a[3]_lut_out, clk, VCC, , , , , , );


--E1L5 is compare8:inst3|reduce_nor~66
--operation mode is normal

E1L5 = C1_b[3] & B1_a[3] & (C1_b[4] $ !B1_a[4]) # !C1_b[3] & !B1_a[3] & (C1_b[4] $ !B1_a[4]);


--C1_b[6] is Reg2:inst1|b[6]
--operation mode is normal

C1_b[6]_lut_out = q_temp[6];
C1_b[6] = DFFEAS(C1_b[6]_lut_out, clk, VCC, , , , , , );


--C1_b[2] is Reg2:inst1|b[2]
--operation mode is normal

C1_b[2]_lut_out = q_temp[2];
C1_b[2] = DFFEAS(C1_b[2]_lut_out, clk, VCC, , , , , , );


--B1_a[2] is Reg1:inst|a[2]
--operation mode is normal

B1_a[2]_lut_out = q[2];
B1_a[2] = DFFEAS(B1_a[2]_lut_out, clk, VCC, , , , , , );


--B1_a[6] is Reg1:inst|a[6]
--operation mode is normal

B1_a[6]_lut_out = q[6];
B1_a[6] = DFFEAS(B1_a[6]_lut_out, clk, VCC, , , , , , );


--E1L6 is compare8:inst3|reduce_nor~67
--operation mode is normal

E1L6 = C1_b[6] & B1_a[6] & (C1_b[2] $ !B1_a[2]) # !C1_b[6] & !B1_a[6] & (C1_b[2] $ !B1_a[2]);


--E1L7 is compare8:inst3|reduce_nor~68
--operation mode is normal

E1L7 = E1L3 & E1L4 & E1L5 & E1L6;


--E1L1 is compare8:inst3|fa~3
--operation mode is normal

E1L1 = G1_cout2 # E1L7;


--E1L2 is compare8:inst3|fb~10
--operation mode is normal

E1L2 = E1L7 & (!G1_cout2);


--H1_cout3 is cnt30:inst6|cout3
--operation mode is normal

H1_cout3_lut_out = H1L31;
H1_cout3 = DFFEAS(H1_cout3_lut_out, clk, VCC, , G1_cout2, , , , );


--A1L81 is inst12~76
--operation mode is normal

A1L81 = clk6 & (H1_cout3 # !E1L7);


--G1_c_temp[3] is cnt10:inst5|c_temp[3]
--operation mode is normal

G1_c_temp[3]_lut_out = !E1L7 & !G1L9 & (G1_c_temp[3] $ G1L1);
G1_c_temp[3] = DFFEAS(G1_c_temp[3]_lut_out, clk, VCC, , inst9, , , , );


--G1_c_temp[2] is cnt10:inst5|c_temp[2]
--operation mode is normal

G1_c_temp[2]_lut_out = !E1L7 & !G1L9 & (G1_c_temp[2] $ G1L2);
G1_c_temp[2] = DFFEAS(G1_c_temp[2]_lut_out, clk, VCC, , inst9, , , , );


--G1_c_temp[1] is cnt10:inst5|c_temp[1]
--operation mode is normal

G1_c_temp[1]_lut_out = !E1L7 & !G1L9 & (G1_c_temp[1] $ G1_c_temp[0]);
G1_c_temp[1] = DFFEAS(G1_c_temp[1]_lut_out, clk, VCC, , inst9, , , , );


--G1_c_temp[0] is cnt10:inst5|c_temp[0]
--operation mode is normal

G1_c_temp[0]_lut_out = !E1L7 & !G1_c_temp[0] & !G1L9;
G1_c_temp[0] = DFFEAS(G1_c_temp[0]_lut_out, clk, VCC, , inst9, , , , );


--H1_d_temp[4] is cnt30:inst6|d_temp[4]
--operation mode is normal

H1_d_temp[4]_carry_eqn = H1L01;
H1_d_temp[4]_lut_out = H1_d_temp[4] $ (!H1_d_temp[4]_carry_eqn);
H1_d_temp[4] = DFFEAS(H1_d_temp[4]_lut_out, clk, VCC, , H1L21, , , , );


--H1_d_temp[3] is cnt30:inst6|d_temp[3]
--operation mode is arithmetic

H1_d_temp[3]_carry_eqn = H1L8;
H1_d_temp[3]_lut_out = H1_d_temp[3] $ (H1_d_temp[3]_carry_eqn);
H1_d_temp[3] = DFFEAS(H1_d_temp[3]_lut_out, clk, VCC, , H1L21, , , , );

--H1L01 is cnt30:inst6|d_temp[3]~111
--operation mode is arithmetic

H1L01 = CARRY(!H1L8 # !H1_d_temp[3]);


--H1_d_temp[2] is cnt30:inst6|d_temp[2]
--operation mode is arithmetic

H1_d_temp[2]_carry_eqn = H1L6;
H1_d_temp[2]_lut_out = H1_d_temp[2] $ (!H1_d_temp[2]_carry_eqn);
H1_d_temp[2] = DFFEAS(H1_d_temp[2]_lut_out, clk, VCC, , H1L21, , , , );

--H1L8 is cnt30:inst6|d_temp[2]~115
--operation mode is arithmetic

H1L8 = CARRY(H1_d_temp[2] & (!H1L6));


--H1_d_temp[1] is cnt30:inst6|d_temp[1]
--operation mode is arithmetic

H1_d_temp[1]_carry_eqn = H1L4;
H1_d_temp[1]_lut_out = H1_d_temp[1] $ (H1_d_temp[1]_carry_eqn);
H1_d_temp[1] = DFFEAS(H1_d_temp[1]_lut_out, clk, VCC, , H1L21, , , , );

--H1L6 is cnt30:inst6|d_temp[1]~119
--operation mode is arithmetic

H1L6 = CARRY(!H1L4 # !H1_d_temp[1]);


--H1_d_temp[0] is cnt30:inst6|d_temp[0]
--operation mode is arithmetic

H1_d_temp[0]_lut_out = !H1_d_temp[0];
H1_d_temp[0] = DFFEAS(H1_d_temp[0]_lut_out, clk, VCC, , H1L21, , , , );

--H1L4 is cnt30:inst6|d_temp[0]~123
--operation mode is arithmetic

H1L4 = CARRY(H1_d_temp[0]);


--G1L9 is cnt10:inst5|cout2_temp~20
--operation mode is normal

G1L9 = G1_c_temp[3] & G1_c_temp[0] & !G1_c_temp[2] & !G1_c_temp[1];


--D1L1 is or88:inst2|qout~46
--operation mode is normal

D1L1 = q_temp[1] # q_temp[7] # q_temp[0] # q_temp[5];


--D1L2 is or88:inst2|qout~47
--operation mode is normal

D1L2 = q_temp[3] # q_temp[4] # q_temp[6] # q_temp[2];


--inst9 is inst9
--operation mode is normal

inst9 = !G1_cout2 & (D1L1 # D1L2);


--H1L31 is cnt30:inst6|LessThan~58
--operation mode is normal

H1L31 = !H1_d_temp[1] # !H1_d_temp[2] # !H1_d_temp[3] # !H1_d_temp[4];


--G1L1 is cnt10:inst5|add~111
--operation mode is normal

G1L1 = G1_c_temp[2] & G1_c_temp[1] & G1_c_temp[0];


--G1L2 is cnt10:inst5|add~112
--operation mode is normal

G1L2 = G1_c_temp[1] & G1_c_temp[0];


--H1L21 is cnt30:inst6|d_temp[4]~4
--operation mode is normal

H1L21 = G1_cout2 & H1L31;


--clk4 is clk4
--operation mode is input

clk4 = INPUT();


--clk6 is clk6
--operation mode is input

clk6 = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--q_temp[1] is q_temp[1]
--operation mode is input

q_temp[1] = INPUT();


--q_temp[7] is q_temp[7]
--operation mode is input

q_temp[7] = INPUT();


--q_temp[0] is q_temp[0]
--operation mode is input

q_temp[0] = INPUT();


--q_temp[5] is q_temp[5]
--operation mode is input

q_temp[5] = INPUT();


--q_temp[3] is q_temp[3]
--operation mode is input

q_temp[3] = INPUT();


--q_temp[4] is q_temp[4]
--operation mode is input

q_temp[4] = INPUT();


--q_temp[6] is q_temp[6]
--operation mode is input

q_temp[6] = INPUT();


--q_temp[2] is q_temp[2]
--operation mode is input

q_temp[2] = INPUT();


--q[7] is q[7]
--operation mode is input

q[7] = INPUT();


--q[1] is q[1]
--operation mode is input

q[1] = INPUT();


--q[5] is q[5]
--operation mode is input

q[5] = INPUT();


--q[0] is q[0]
--operation mode is input

q[0] = INPUT();


--q[4] is q[4]
--operation mode is input

q[4] = INPUT();


--q[3] is q[3]
--operation mode is input

q[3] = INPUT();


--q[2] is q[2]
--operation mode is input

q[2] = INPUT();


--q[6] is q[6]
--operation mode is input

q[6] = INPUT();


--fa is fa
--operation mode is output

fa = OUTPUT(!E1L1);


--fb is fb
--operation mode is output

fb = OUTPUT(E1L2);


--police11 is police11
--operation mode is output

police11 = OUTPUT(A1L81);


--c[3] is c[3]
--operation mode is output

c[3] = OUTPUT(G1_c_temp[3]);


--c[2] is c[2]
--operation mode is output

c[2] = OUTPUT(G1_c_temp[2]);


--c[1] is c[1]
--operation mode is output

c[1] = OUTPUT(G1_c_temp[1]);


--c[0] is c[0]
--operation mode is output

c[0] = OUTPUT(G1_c_temp[0]);


--d[4] is d[4]
--operation mode is output

d[4] = OUTPUT(H1_d_temp[4]);


--d[3] is d[3]
--operation mode is output

d[3] = OUTPUT(H1_d_temp[3]);


--d[2] is d[2]
--operation mode is output

d[2] = OUTPUT(H1_d_temp[2]);


--d[1] is d[1]
--operation mode is output

d[1] = OUTPUT(H1_d_temp[1]);


--d[0] is d[0]
--operation mode is output

d[0] = OUTPUT(H1_d_temp[0]);


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