cnt1.vhd

来自「实现电子密码锁的各项功能,经过编译和仿真」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt1 is
port(clk9,clr:in std_logic;
     enn:in std_logic;
      ccout:buffer std_logic;
     qqout:buffer std_logic_vector(1 downto 0));
end cnt1;
architecture one of cnt1 is
 begin 
   process(clk9,enn)
     begin  
       if clr='0' then
          qqout<="00";
			ccout<='0';
          elsif clk9'event and clk9='1' then 
           if enn='1' then 
              if qqout<1 then 
                qqout<=qqout+1;
                   ccout<='1';
                 else  ccout<='0';
             end if;
					else  ccout<='0';
             end if;
		end if;
          end process;
 end one;