total.hier_info

数字显示当前的小时、分钟、秒； 2、可以预置为12小时计时显示和24小时计时显示； 3、一个调节键

|TOTAL
MOEDL_SHOW <= HOUR:inst3.MODEL_OUT
CLOCK_MAICHONG => CLK_CHOOSE:inst2.CLK_MC
CLK_1KHZ => fenp:inst9.clk1k
CLK_1KHZ => SELTIME:inst5.CLK
RESET => SECOND:inst1.RESET
RESET => MINUTE:inst.RESET
RESET => HOUR:inst3.RESET
SET_TIME[0] => CLK_CHOOSE:inst2.SET_TIME[0]
SET_TIME[1] => CLK_CHOOSE:inst2.SET_TIME[1]
MODEL_INPUT => HOUR:inst3.MODEL
ALERT_OUTPUT <= inst7.DB_MAX_OUTPUT_PORT_TYPE
CLK_2KHZ => inst7.IN0
DAOUT[0] <= SELTIME:inst5.DAOUT[0]
DAOUT[1] <= SELTIME:inst5.DAOUT[1]
DAOUT[2] <= SELTIME:inst5.DAOUT[2]
DAOUT[3] <= SELTIME:inst5.DAOUT[3]
SEL_TIME[0] <= SELTIME:inst5.SEL[0]
SEL_TIME[1] <= SELTIME:inst5.SEL[1]
SEL_TIME[2] <= SELTIME:inst5.SEL[2]


|TOTAL|HOUR:inst3
CLK => CQI[7].CLK
CLK => CQI[6].CLK
CLK => CQI[5].CLK
CLK => CQI[4].CLK
CLK => CQI[3].CLK
CLK => CQI[2].CLK
CLK => CQI[1].CLK
CLK => CQI[0].CLK
RESET => CQI[7].ACLR
RESET => CQI[6].ACLR
RESET => CQI[5].ACLR
RESET => CQI[4].ACLR
RESET => CQI[3].ACLR
RESET => CQI[2].ACLR
RESET => CQI[1].ACLR
RESET => CQI[0].ACLR
MODEL => LessThan0.IN8
MODEL => MODEL_OUT.DATAIN
MODEL => LessThan0.IN6
MODEL => LessThan0.IN7
HOUR0[0] <= CQI[0].DB_MAX_OUTPUT_PORT_TYPE
HOUR0[1] <= CQI[1].DB_MAX_OUTPUT_PORT_TYPE
HOUR0[2] <= CQI[2].DB_MAX_OUTPUT_PORT_TYPE
HOUR0[3] <= CQI[3].DB_MAX_OUTPUT_PORT_TYPE
HOUR1[0] <= CQI[4].DB_MAX_OUTPUT_PORT_TYPE
HOUR1[1] <= CQI[5].DB_MAX_OUTPUT_PORT_TYPE
HOUR1[2] <= CQI[6].DB_MAX_OUTPUT_PORT_TYPE
HOUR1[3] <= CQI[7].DB_MAX_OUTPUT_PORT_TYPE
MODEL_OUT <= MODEL.DB_MAX_OUTPUT_PORT_TYPE


|TOTAL|CLK_CHOOSE:inst2
CLK_MC => Mux2.IN2
CLK_MC => Mux1.IN2
CLK_MC => Mux0.IN2
CLK_1HZ => Mux0.IN3
SEC_COUT => Mux1.IN3
MIN_COUT => Mux2.IN3
SET_TIME[0] => Mux2.IN5
SET_TIME[0] => Mux1.IN5
SET_TIME[0] => Mux0.IN5
SET_TIME[1] => Mux2.IN4
SET_TIME[1] => Mux1.IN4
SET_TIME[1] => Mux0.IN4
HOUR_CLK <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
MIN_CLK <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
SEC_CLK <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|TOTAL|fenp:inst9
cp1hz <= 7490:12.QD
clk1k => 7490:10.CLKA


|TOTAL|fenp:inst9|7490:12
QA <= 7.DB_MAX_OUTPUT_PORT_TYPE
CLRA => 9.IN0
CLRB => 9.IN1
CLKA => 32.IN0
SET9A => 8.IN0
SET9B => 8.IN1
QB <= 11.DB_MAX_OUTPUT_PORT_TYPE
CLKB => 33.IN0
QC <= 14.DB_MAX_OUTPUT_PORT_TYPE
QD <= 19.DB_MAX_OUTPUT_PORT_TYPE


|TOTAL|fenp:inst9|7490:11
QA <= 7.DB_MAX_OUTPUT_PORT_TYPE
CLRA => 9.IN0
CLRB => 9.IN1
CLKA => 32.IN0
SET9A => 8.IN0
SET9B => 8.IN1
QB <= 11.DB_MAX_OUTPUT_PORT_TYPE
CLKB => 33.IN0
QC <= 14.DB_MAX_OUTPUT_PORT_TYPE
QD <= 19.DB_MAX_OUTPUT_PORT_TYPE


|TOTAL|fenp:inst9|7490:10
QA <= 7.DB_MAX_OUTPUT_PORT_TYPE
CLRA => 9.IN0
CLRB => 9.IN1
CLKA => 32.IN0
SET9A => 8.IN0
SET9B => 8.IN1
QB <= 11.DB_MAX_OUTPUT_PORT_TYPE
CLKB => 33.IN0
QC <= 14.DB_MAX_OUTPUT_PORT_TYPE
QD <= 19.DB_MAX_OUTPUT_PORT_TYPE


|TOTAL|SECOND:inst1
CLK => CNT1[3].CLK
CLK => CNT1[2].CLK
CLK => CNT1[1].CLK
CLK => CNT1[0].CLK
CLK => CNT0[3].CLK
CLK => CNT0[2].CLK
CLK => CNT0[1].CLK
CLK => CNT0[0].CLK
CLK => COUT~reg0.CLK
RESET => CNT1[3].ACLR
RESET => CNT1[2].ACLR
RESET => CNT1[1].ACLR
RESET => CNT1[0].ACLR
RESET => CNT0[3].ACLR
RESET => CNT0[2].ACLR
RESET => CNT0[1].ACLR
RESET => CNT0[0].ACLR
RESET => COUT~reg0.ENA
SECOND0[0] <= CNT0[0].DB_MAX_OUTPUT_PORT_TYPE
SECOND0[1] <= CNT0[1].DB_MAX_OUTPUT_PORT_TYPE
SECOND0[2] <= CNT0[2].DB_MAX_OUTPUT_PORT_TYPE
SECOND0[3] <= CNT0[3].DB_MAX_OUTPUT_PORT_TYPE
SECOND1[0] <= CNT1[0].DB_MAX_OUTPUT_PORT_TYPE
SECOND1[1] <= CNT1[1].DB_MAX_OUTPUT_PORT_TYPE
SECOND1[2] <= CNT1[2].DB_MAX_OUTPUT_PORT_TYPE
SECOND1[3] <= CNT1[3].DB_MAX_OUTPUT_PORT_TYPE
COUT <= COUT~reg0.DB_MAX_OUTPUT_PORT_TYPE


|TOTAL|MINUTE:inst
CLK => CNT1[3].CLK
CLK => CNT1[2].CLK
CLK => CNT1[1].CLK
CLK => CNT1[0].CLK
CLK => CNT0[3].CLK
CLK => CNT0[2].CLK
CLK => CNT0[1].CLK
CLK => CNT0[0].CLK
CLK => COUT~reg0.CLK
RESET => CNT1[3].ACLR
RESET => CNT1[2].ACLR
RESET => CNT1[1].ACLR
RESET => CNT1[0].ACLR
RESET => CNT0[3].ACLR
RESET => CNT0[2].ACLR
RESET => CNT0[1].ACLR
RESET => CNT0[0].ACLR
RESET => COUT~reg0.ENA
MIN1[0] <= CNT1[0].DB_MAX_OUTPUT_PORT_TYPE
MIN1[1] <= CNT1[1].DB_MAX_OUTPUT_PORT_TYPE
MIN1[2] <= CNT1[2].DB_MAX_OUTPUT_PORT_TYPE
MIN1[3] <= CNT1[3].DB_MAX_OUTPUT_PORT_TYPE
MIN0[0] <= CNT0[0].DB_MAX_OUTPUT_PORT_TYPE
MIN0[1] <= CNT0[1].DB_MAX_OUTPUT_PORT_TYPE
MIN0[2] <= CNT0[2].DB_MAX_OUTPUT_PORT_TYPE
MIN0[3] <= CNT0[3].DB_MAX_OUTPUT_PORT_TYPE
COUT <= COUT~reg0.DB_MAX_OUTPUT_PORT_TYPE


|TOTAL|ALERT:inst6
MIN1[0] => Equal0.IN2
MIN1[1] => Equal0.IN0
MIN1[2] => Equal0.IN3
MIN1[3] => Equal0.IN1
MIN0[0] => Equal1.IN2
MIN0[1] => Equal1.IN0
MIN0[2] => Equal1.IN1
MIN0[3] => Equal1.IN3
SECOND1[0] => Equal2.IN2
SECOND1[1] => Equal2.IN0
SECOND1[2] => Equal2.IN3
SECOND1[3] => Equal2.IN1
SECOND0[0] => Equal3.IN2
SECOND0[1] => Equal3.IN0
SECOND0[2] => Equal3.IN1
SECOND0[3] => Equal3.IN3
CLK => QLK~reg0.CLK
QLK <= QLK~reg0.DB_MAX_OUTPUT_PORT_TYPE


|TOTAL|SELTIME:inst5
CLK => COUNT[2].CLK
CLK => COUNT[1].CLK
CLK => COUNT[0].CLK
SEC1[0] => Mux3.IN0
SEC1[1] => Mux2.IN0
SEC1[2] => Mux1.IN0
SEC1[3] => Mux0.IN0
SEC0[0] => Mux3.IN1
SEC0[1] => Mux2.IN1
SEC0[2] => Mux1.IN1
SEC0[3] => Mux0.IN1
MIN1[0] => Mux3.IN2
MIN1[1] => Mux2.IN2
MIN1[2] => Mux1.IN2
MIN1[3] => Mux0.IN2
MIN0[0] => Mux3.IN3
MIN0[1] => Mux2.IN3
MIN0[2] => Mux1.IN3
MIN0[3] => Mux0.IN3
H1[0] => Mux3.IN4
H1[0] => Mux3.IN5
H1[0] => Mux3.IN6
H1[1] => Mux2.IN4
H1[1] => Mux2.IN5
H1[1] => Mux2.IN6
H1[2] => Mux1.IN4
H1[2] => Mux1.IN5
H1[2] => Mux1.IN6
H1[3] => Mux0.IN4
H1[3] => Mux0.IN5
H1[3] => Mux0.IN6
H0[0] => Mux3.IN7
H0[1] => Mux2.IN7
H0[2] => Mux1.IN7
H0[3] => Mux0.IN7
DAOUT[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
DAOUT[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
DAOUT[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
DAOUT[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
SEL[0] <= COUNT[0].DB_MAX_OUTPUT_PORT_TYPE
SEL[1] <= COUNT[1].DB_MAX_OUTPUT_PORT_TYPE
SEL[2] <= COUNT[2].DB_MAX_OUTPUT_PORT_TYPE