total.tan.talkback.xml

数字显示当前的小时、分钟、秒； 2、可以预置为12小时计时显示和24小时计时显示； 3、一个调节键

<!--
This XML file (created on Wed Oct 29 23:40:25 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<nic_id>001e9006b92f</nic_id>
	<cdrive_id>c8766079</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Web Edition</edition>
	<eval>Eval</eval>
	<compilation_end_time>Wed Oct 29 23:40:26 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">2099</cpu_freq>
	</cpu>
	<ram units="MB">768</ram>
</machine>
<top_file>J:/ALL/TOTAL</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off TOTAL -c TOTAL --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Circuit may not operate. Detected 111 non-operational path(s) clocked by clock &quot;CLOCK_MAICHONG&quot; with clock skew larger than data delay. See Compilation Report for details.</warning>
	<warning>Warning: Circuit may not operate. Detected 111 non-operational path(s) clocked by clock &quot;SET_TIME[1]&quot; with clock skew larger than data delay. See Compilation Report for details.</warning>
	<warning>Warning: Circuit may not operate. Detected 111 non-operational path(s) clocked by clock &quot;SET_TIME[0]&quot; with clock skew larger than data delay. See Compilation Report for details.</warning>
	<warning>Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 5 warnings</info>
	<info>Info: Elapsed time: 00:00:03</info>
	<info>Info: Processing ended: Wed Oct 29 23:40:24 2008</info>
	<info>Info: th for register &quot;HOUR:inst3|CQI[4]&quot; (data pin = &quot;MODEL_INPUT&quot;, clock pin = &quot;CLOCK_MAICHONG&quot;) is 10.200 ns</info>
	<info>Info: - Shortest pin to register delay is 8.670 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>CLOCK_1HZ</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>SET_TIME[0]</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>SET_TIME[1]</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>CLOCK_MAICHONG</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>CLK_0HZ</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>1.162 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>26.017 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tpd</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>8.307 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>10.200 ns</actual>
	</nonclk>
	<clk>
		<name>CLOCK_MAICHONG</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>66.06 MHz ( period = 15.137 ns )</actual>
	</clk>
	<clk>
		<name>SET_TIME[1]</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>67.81 MHz ( period = 14.748 ns )</actual>
	</clk>
	<clk>
		<name>SET_TIME[0]</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>69.11 MHz ( period = 14.470 ns )</actual>
	</clk>
	<clk>
		<name>CLOCK_1HZ</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>83.40 MHz ( period = 11.991 ns )</actual>
	</clk>
	<clk>
		<name>CLK_0HZ</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>Restricted to 320.10 MHz ( period = 3.124 ns )</actual>
	</clk>
</performance>
<compile_id>45E72927</compile_id>
</talkback>